Yamaha DVD-S1700 Service Manual page 28

DVD-S1700
No.
Pin Name I/O Type
61 SDRAM DATA(11) Tristate I/O
62 VDD4
63 VSS
64 SDRAM DATA(12) Tristate I/O
65 SDRAM DATA(13) Tristate I/O
66 SDRAM DATA(14) Tristate I/O
67 SDRAM DATA(15) Tristate I/O
68 VDDcore3
69 VSScore
70 SDRAM DATA(16) Tristate I/O
71 SDRAM DATA(17) Tristate I/O
72 SDRAM DATA(18) Tristate I/O
73 SDRAM DATA(19) Tristate I/O
74 SDRAM DATA(20) Tristate I/O
75 SDRAM DATA(21) Tristate I/O
76 SDRAM DATA(22) Tristate I/O
77 SDRAM DATA(23) Tristate I/O
78 SDRAM DATA(24) Tristate I/O
79 SDRAM DATA(25) Tristate I/O
80 VDDcore4
81 VSScore
82 SDRAM DATA(26) Tristate I/O
83 SDRAM DATA(27) Tristate I/O
84 SDRAM DATA(28) Tristate I/O
85 SDRAM DATA(29) Tristate I/O
86 SDRAM DATA(30) Tristate I/O
87 SDRAM DATA(31) Tristate I/O
88 VDD5
89 VSS
90 TEST IN
91 SDRAM ADDR(10) Tristate O/P
92 SDRAM ADDR(9) Tristate O/P
93 SDRAM ADDR(8) Tristate O/P
94 SDRAM ADDR(7) Tristate O/P
95 SDRAM ADDR(6) Tristate O/P
96 VDDcore5
97 VSScor
98 SDRAM ADDR(5) Tristate O/P
99 SDRAM ADDR(4) Tristate O/P
100 SDRAM ADDR(3) Tristate O/P
101 SDRAM ADDR(2) Tristate O/P
102 SDRAM ADDR(1) Tristate O/P
103 SDRAM ADDR(0) Tristate O/P
104 SDRAM WEN Tristate O/P
105 SDRAM RASN Tristate O/P
106 SDRAM CASN Tristate O/P
107 SDRAM BA1 Tristate O/P
108 SDRAM BA0 Tristate O/P
109 SDRAM CSN Tristate O/P
110 SDRAM DQM Tristate O/P
111 SDRAM CLKOUT
112 VDD6
113 VSS
114 SDRAM CLKIN
115 TEST3
116 TEST OUT0
117 TEST OUT1
118 CTLOUT0 Tristate O/P
119 CTLOUT1 Tristate O/P
28
Voltage
Drive
Tolerance
5v 4mA
Power
Ground
5v 4mA
5v 4mA
5v 4mA
5v 4mA
Power
Ground
5v 4mA
5v 4mA
5v 4mA
5v 4mA
5v 4mA
5v 4mA
5v 4mA
5v 4mA
5v 4mA
5v 4mA
Power
Ground
5v 4mA
5v 4mA
5v 4mA
5v 4mA
5v 4mA
5v 4mA
Power
Ground
Input 5v
5v 8mA
5v 8mA
5v 8mA
5v 8mA
5v 8mA
Power
Ground
5v 8mA
5v 8mA
5v 8mA
5v 8mA
5v 8mA
5v 8mA
5v 8mA
5v 8mA
5v 8mA
5v 8mA
5v 8mA
5v 4mA
5v 8mA
Output 5v 12mA
Power
Ground
Input 5v
Input
Output 12mA
Output 8mA
5v 8mA
5v 8mA
Internal
Pull-up/
Pull-down
PD SDRAM data bus *
3.3 V - Power pin for IO
Ground
PD SDRAM data bus *
PD SDRAM data bus *
PD SDRAM data bus *
PD SDRAM data bus *
1.8 V - Power pin for core
Ground
PD SDRAM data bus *
PD SDRAM data bus *
PD SDRAM data bus *
PD SDRAM data bus *
PD SDRAM data bus *
PD SDRAM data bus *
PD SDRAM data bus *
PD SDRAM data bus *
PD SDRAM data bus *
PD SDRAM data bus *
1.8 V - Power pin for core
Ground
PD SDRAM data bus *
PD SDRAM data bus *
PD SDRAM data bus *
PD SDRAM data bus *
PD SDRAM data bus *
PD SDRAM data bus *
3.3 V - Power pin for IO
Ground
Test input - Connect to ground
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
1.8 V - Power pin for core
Ground
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM write enable *
SDRAM row address select *
SDRAM column address select *
SDRAM bank select 1 *
SDRAM bank select 0 *
SDRAM CS *
SDRAM DQM *
Clock out to SDRAM *
3.3 V - Power pin for IO
Ground
Trace delayed SDRAM clock in
Test input -Connect to ground
Test output - Leave open
Test output - Leave open
Control signal output selectable as HSync1/
CSync/HRef/Monitor coast
Control signal output selectable as
Description