Yamaha DVD-S1700 Service Manual page 14

DVD-S1700
No.
Pin Functions Direction
FCUIF[16]
39 MEMDA[8]
FCUIF[21]
40 MEMAD[5]
FCUIF[15]
41 VDDP
42 MEMDA[0]
FCUIF[2]
43 MEMAD[4]
FCUIF[14]
44 MEMRD#
FCUIF[1]
45-46 MEMAD[3, 2]
FCUIF[13, 12]
47 MEMCS[0]#
48 MEMAD[1]
FCUIF[11]
BOOTSEL[2]
49 MEMAD[0]
FCUIF[10]
BOOTSEL[1]
50 GNDP
51 VDD-IP
52 VDDP
53-57 RAMADD
[4, 3, 5, 2, 6]
58 VDDP
59-61 RAMADD
[1, 7, 0]
62 GNDP
63 RAMADD[8]
64 VDDC
65 RAMADD[10]
66 GNDC
67 RAMADD[9]
68 VDDP
69 RAMADD[11]
70 RAMCS[0]#
RAMBA[1]
71 RAMBA[0]
72 GNDP
73 RAMCS[1]#
74 RAMRAS#
75 RAMCAS#
76 VDDP
77 RAMWE#
78 RAMDQM
79 GNDPCLK
80 PCLK
81 VDDPCLK
82 RAMDAT[8]
83 GNDP
84-86 RAMDAT
[7, 9, 6]
87 VDDP
88-90 RAMDAT
[10, 5, 11]
91 GNDP
14
O Flash card interface unit output signal
I/O PNVM/SRAM bi-directional data bus
I/O Flash card interface unit I/O signal
O PNVM/SRAM address bus outputs
O Flash card interface unit output signal
S 3.3 V digital periphery power supply
I/O PNVM/SRAM bi-directional data bus
O Flash card interface unit output signal
I/O PNVM/SRAM address bus outputs
O Flash card interface unit output signal
O PNVM/SRAM read enable (active low) output
I/O Flash card interface unit I/O signal
O PNVM/SRAM address bus outputs
O Flash card interface unit output signal
O PNVM/SRAM chip select (active low) output
O PNVM/SRAM address bus outputs
O Flash card interface unit output signals
I Microprocessor SW boot (and execute) source selection:
(high, high) - For production testing;
(high, low) - Flash+SRAM (for debug monitor);
(low, high) - First debug UART
(low, low) - Flash (low) or Level sampled during RESET
O PNVM/SRAM address bus outputs
O Flash card interface unit output signals
I Microprocessor SW boot (and execute) source selection:
(high, high) - For production testing;
(high, low) - Flash+SRAM (for debug monitor);
(low, high) - First debug UART
(low, low) - Flash (low) or Level sampled during RESET
S Digital periphery ground of 3.3 V supply
S 3.3 V periphery reference voltage
S 3.3 V digital periphery power supply
O SDRAM address bus output
S 3.3 V digital periphery power supply
O SDRAM address bus output
S Digital periphery ground of 3.3 V supply
O SDRAM address bus output
S 1.8 V digital core power supply
O SDRAM address bus output
S Digital core ground of 1.8 V supply
O SDRAM address bus output
S 3.3 V digital periphery power supply
O SDRAM address bus output
O SDRAM chip select (active low)
O SDRAM bank select output
O SDRAM bank select output
S Digital periphery ground of 3.3 V supply
O SDRAM chip select (active low) output
O SDRAM row select (active low) output
O SDRAM column select (active low) output
S 3.3 V digital periphery power supply
O SDRAM write enable (active low) output
O SDRAM data masking (active high) output
S Digital ground of filtered 3.3 V supply for PCLK
O SDRAM clock output (same as internal processing clock)
S 3.3 V filtered digital power supply for PCLK
I/O SDRAM bi-directional data bus
S Digital periphery ground of 3.3 V supply
I/O SDRAM bi-directional data bus
S 3.3 V digital periphery power supply
I/O SDRAM bi-directional data bus
S Digital periphery ground of 3.3 V supply
Description