LG F1200 Service Manual page 16

3. TECHNICAL BRIEF
Figure 2. SYNTHESIZER PART Block Diagram
(1) DCXO
The Aero I+ transceiver integrates the DCXO circuitry required to generate a precise system
reference clock using only an external crystal resonator. (See Figure 15.) An internal digitally
programmable capacitor array (CDAC) provides a coarse method of adjusting the reference
frequency in discrete steps. An integrated analog varactor (CVAR) allows for a fine and
continuous adjustment of the reference frequency by an external control voltage (XAFC). This
control voltage is supplied by the AFC DAC on the baseband IC. The complete DCXO solution
effectively replaces TCVCXO modules typically required to provide a 13 or 26 MHz reference
clock for the system.
Figure 3. DCXO
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