Synthesizer Part - LG F1200 Service Manual

3. TECHNICAL BRIEF
(2) Low IF
A quadrate image-rejection mixer downconverts the RF signal to a 100kHz intermediate
frequency (IF) with the RFLO. The RFLO frequency is between 1849.8 and 1918.8 MHz, and is
divided by two for EGSM modes. The RFLO frequency is between 1804.9 and 1879.9 MHz, and
is divided by one for DCS modes. The RFLO frequency is between 1929.9 and 1989.9 MHz,
and is divided by one for PCS modes. The mixer output is amplified with an analog
programmable gain amplifier (PGA), which is controlled with the AGAIN[2:0] bits in register 05h.
The quadrate IF signal is digitized with high resolution A/D converters (ADCs). The
Si4206[U101] down-converts the ADC output to baseband with a digital 100kHz quadrate LO
signal. Digital decimation and IIR filters perform channel selection to remove blocking and
reference interference signals. The response of the IIR filter is programmable to a high
selectivity setting (CSEL=0) or a low selectivity setting (CSEL=1). After channel selection, the
digital output is scaled with digital PGA, which is controlled with the DGAIN[5:0] bits in register
05h.
(3) Demodulator and Baseband Processing
The amplified digital output signal go through with DACs that drive a differential analog signal
onto the RXIP, RXIN, RXQP and RXQN pins to interface to standard analog ADC input
baseband ICs. No special processing is required in the baseband for offset compensation or
extended dynamic range. Compared to a direct-conversion architecture, the low-IF architecture
has a much greater degree of immunity to dc offsets that can arise from RF local oscillator
(RFLO) self-mixing, 2nd order distortion of blockers, and device 1/f noise.

3.3 Synthesizer Part

The Si4206[U101] integrates two complete PLLs including VCOs, varactors, resonators, loop
filters, reference and VCO dividers, and phase detectors. The RF PLL uses two multiplexed
VCOs. The RF1 VCO is used for receive mode, and the RF2 VCO is used for transmit mode.
The IF PLL is used only during transmit mode. All VCO tuning inductors are also integrated. The
IF and RF output frequencies are set by programming the N-Divider registers, N
N . Programming the N-Divider register for either RF1 or RF2 automatically selects the proper
IF
VCO. The output frequency of each PLL is as follows:
A programmable divider in the input stage allows either a 13 or 26 MHz reference frequency
depending on the choice of crystal. A 26 MHz reference clock can be divided by 2 using the
DIV2 bit in Register 31h. The RF PLL phase detector update rate (f ) can be programmed with
the RFUP bit in register 31h to either f
= 200 kHz. Receive mode should use f
= 200 kHz in the E-GSM 900 bands. Transmit modes should always use f
F = N x f
OUT
= 100 kHz or f = 200 kHz. The IF PLL always uses f
= 100 kHz in DCS 1800 and PCS 1900 bands, and f
- 14 -
, N , and
RF1 RF2
= 200 kHz.