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IMAGE SENSOR SOLUTIONS
KAI-2001/KAI-2020/KAI-2093 IMAGER BOARD ARCHITECTURE OVERVIEW
The following sections describe the functional blocks of the Imager board (refer to Figure 1).
Power Filtering And Regulation
Power is supplied to the Imager Board via the J4
interface connector. The power supplies are de-
coupled and filtered with ferrite beads and
capacitors to suppress noise. Voltage regulators
are used to create the +15 and –15V supplies from
the VPLUS and VMINUS supplies.
LVDS Receivers / TTL Buffers
LVDS timing signals are input to the Imager Board
via the J4 interface connector. These signals are
shifted to TTL levels before being sent to the CCD
clock drivers.
CCD Pixel-Rate Clock Drivers (H1, H2 &
Reset Clocks)
The pixel rate CCD clock drivers utilize two fast
switching transistors that are designed to translate
TTL-level input clock signals to the voltage levels
required by the CCD.
levels
of
the
potentiometers, and are buffered by operational
amplifiers configured as voltage followers.
Reset Clock One-Shot
The pulse width of the RESET_CCD clock may be
set by U13, a programmable One-Shot. The One-
Shot can be configured to provide a RESET_CCD
clock signal with a pulse width from 5ns to 15ns. If
pulse width control functionality is provided by the
Timing Board, the One-Shot may be removed and
bypassed by installing R147.
CCD VCLK Drivers
The vertical clock (VCLK) drivers consist of
MOSFET driver IC's. These drivers are designed
to translate the TTL-level clock signals to the
voltage levels required by the CCD.
middle, and low voltage levels of the vertical
clocks are set by potentiometers buffered by
operational amplifiers. The VHIGH and VLOW op-
amps have a gain of 1.25, to allow the magnitude
of the voltages to be adjusted to 12.5V when using
DAC control.
The current sources for these voltage levels are
high current (up to 600 mA) transistors. The
V2_CCD high level clock voltage is switched from
V_MID to V_HIGH once per frame to transfer the
charge from the photodiodes to the vertical CCDs.
M T D / P S - 0 7 1 5
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The high level and low
CCD
clocks
are
set
The high,
5 8 5 - 7 2 2 - 4 3 8 5
The V1 clock driver is a 2-level driver circuit,
switching between VMID amd VLOW voltage
levels.
CCD FDG DRIVER
The Fast Dump clock drivers consist of a transistor
that will switch the voltage on the FD pin of the
CCD from FDG_LOW to FDG_HIGH during Fast
Dump Gate operations. When not in operation, or
when the Fast Dump Gate feature is not being
utilized, the FDG pin of the CCD is held at
FDG_LOW.
voltage levels of the FDG driver are set by
potentiometers, buffered by operational amplifiers
configured as voltage followers.
The KAI-2093 image sensor does not have the
Fast Dump Gate feature. To support this device,
the Imager Board must be configured so that the
CCD pin 11 is 0.0V. To accomplish this, R91 is
removed, and R79 is installed.
by
VSUB/VES CIRCUIT
The quiescent CCD substrate voltage (VSUB) is
set by a potentiometer and resistor divider
network.
The VSUB voltage is buffered by an
operational amplifier configured with a gain of
1.40, to allow the voltage to be adjusted to nearly
14.0V. A blocking diode prevents the VSUB bias
circuitry from being damaged by the higher-voltage
electronic shutter pulse.
For electronic shutter operation, the VES signal
drives a transistor amplifier circuit that AC-couples
the voltage difference between the VPLUS and
VMINUS supplies onto the Substrate voltage. This
creates the necessary potential to clear all charge
from the photodiodes, thereby acting as an
electronic shutter to control exposure.
VDD Bias Voltage
The VDDL and VDDR video output amplifier
supplies in the CCD are coupled directly to the
+15V regulated supply on the Imager Board. The
Imager Board contains optional circuitry that
allows this voltage to be adjusted through the
Alternate VDD bias circuit.
The Imager Board contains optional Amplifier
Enable circuitry to control a switch that switches
the VDD voltage from +15V to ALT_VDD.
F a x : 5 8 5 - 4 7 7 - 4 9 4 7
P a g e 5 o f 3 1
The FDG_HIGH and FDG_LOW
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