EE Tools MaxLoader User Manual page 114

MaxLoader User's Guide
DIP
FPGA
Functional Test
Fuse
GAL
Gang Programmer A multiple-socket programmer that requires each device to be placed in a
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connected to the external metal interconnect pins of the IC with very small
bonding wires. It can be seen through the window of erasable EPROMs.
Dual Inline Package. An IC package with two rows of through-hole pins,
usually on 0.1 pitch, 0.3 or 0.6 inches apart.
Field Programmable Gate Array. A very complex PLD. The FPGA usually
has an architecture that comprises a large number of simple logic blocks, a
number of input/output pads, and a method to make random connections
between the elements.
A test that is performed following the programming of a PLD. The test
operates the device in its normal operating mode by simulating the inputs
and outputs that the part will experience in normal operation. To perform the
test, the engineer must supply a set of test vectors that describe normal
operation of the device so the device programmer can apply the specified
stimulus and verify that the device is operating as designed. It is important to
perform a functional test on PLDs because, in many cases, the PLD cannot
be fully tested at the factory before programming so a defective PLD may
program correctly but fail the functional test. A properly designed functional
test will verify that the part meets the design specification, ensuring that the
device, the compiler, the programmer, and the engineer have all performed
their respective tasks correctly.
A metal connection within a PLD or memory that may be melted during
programming to break the circuit. These links typically carry input signals to
logic gates. Burning all the fuses except those that are required in the desired
circuit forms the desired circuit configuration. Since the fuses cannot be
tested nondestructively, fuse-like programmable devices cannot be 100%
tested at the factory and consequently expected programming yields are
usually 98-99%.
Generic Array Logic. EEPROM based second generation PAL devices.
socket before any can be programmed. See Concurrent Programmer.