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TECHNICAL SERVICE MANUAL
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Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed
concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume
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Power-down features to conserve energy in battery-powered applications include: automatic device power
down during suspend, PCI power management for link-layer and inactive ports powered down, ultra low-
power sleep mode
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Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s
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Cable power presence monitoring
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Separate cable bias (TPBIAS) for each port
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Physical write posting of up to three outstanding transactions
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PCI burst transfers and deep FIFO to tolerate large host latency
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External cycle timer control for customized synchronization
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Extended resume signaling for compatibility with legacy DV components
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PHY-Link logic performs system initialization and arbitration functions
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PHY-Link encode and decode functions included for data-strobe bit level encoding
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PHY-Link incoming data resynchronized to local clock
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Prestigio Nobile 1510
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