Read/Write Asic - Maxtor D740X-6L 20.0 AT Product Manual

B a s i c P r i n c i p l e s o f O p e r a t i o n
The integrated µProcessor, Disk Controller, and ATA Interface Electronics have nine
functional modules (described below):
• µProcessor
• Digital Synchronous Spoke (DSS)
• Error Correction Code (ECC) Control
• Formatter
• Buffer Controller
• Servo Controller, including PWM
• Serial Interface
• ATA Interface Controller
• Motor Controller
       z 2 T Q E G U U Q T
The µProcessor core provides local processor services to the drive electronics under
program control. The µProcessor manages the resources of the Disk Controller, and
ATA Interface internally. It also manages the Read/Write ASIC (Application Specific
Integrated Circuit), and the Spindle/VCM driver externally.
       & K I K V C N 5 [ P E J T Q P Q W U 5 R Q M G
The DSS decodes servo information written on the drive at the factory to determine
the position of the read/write head. It interfaces with the read/write channel, process
timing and position information, and stores it in registers that are read by the servo
firmware.
       ' T T Q T % Q T T G E V K Q P % Q F G ' % % % Q P V T Q N
The Error Correction Code (ECC) Control block utilizes a Reed-Solomon encoder/
decoder circuit that is used for disk read/write operations. It uses a total of 44
redundancy bytes organized as 40 ECC (Error Correction Code) bytes with one
interleave, and four cross-check bytes. The ECC uses ten bits per symbol and one
interleave. This is guaranteed to correct 150 bits and as many as 160 bits in error.
       ( Q T O C V V G T
The Formatter controls the operation of the read and write channel portions of the
ASIC. To initiate a disk operation, the µProcessor loads a set of commands into the
WCS (writable control store) register. Loading and manipulating the WCS is done
through the µProcessor Interface registers.
The Formatter also directly drives the read and write gates (
Mode Interface of the Read/Write ASIC and the R/W Preamplifier, as well as passing
write data to the Precompensator circuit in the Read/Write ASIC.
       $ W H H G T % Q P V T Q N N G T
The Buffer Controller supports a 2MB buffer, which is organized as 1M x 16 bits. The
16-bit width implementation provides a 233MB/s maximum buffer bandwidth. This
increased bandwidth allows the µProcessor to have direct access to the buffer,
eliminating the need for a separate µProcessor RAM IC.
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, ) and Command
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