SOYO SY-P4X400 DRAGON Lite User Manual page 63

BIOS Setup Utility
3-4.2 CPU & PCI Bus Control
Caution: Change these settings only if you are already familiar
with the Chipset.
The [CPU & PCI Bus Control] option changes the values of the chipset
registers. These registers control the system options in the computer.
CMOS Setup Utility – Copyright ( C ) 1984-2002 Award Software
CPU to PCI Write Buffer
PCI Master 0 WS Write
PCI Delay Transaction
VLink 8X Support
:Move Enter:Select
F5:Previous Values
After you have completed the changes, press [Esc] and follow the
instructions on your screen to save your settings or exit without saving.
CPU & PCI Bus Control
Setting
CPU to PCI Disabled
Write Buffer
Enabled
Disabled
PCI Master 0
WS Write
Enabled
PCI Delay Disabled
Transaction Enabled
Disabled
VLink 8X
Support
Enabled
CPU & PCI Bus Control
Enabled
Enabled
Disabled
Enabled
+/-/PU/PD:Value F10:Save
F6:Fail-Safe Defaults
Description
Enabled the CPU to PCI Write
Buffer.
This item allows you to
enabled/disabled the PCI post write. Default
The chipset has an embedded 32-bit
posted write buffer to support delay
transactions cycles. Select Enabled
to support compliance with PCI
specification version 2.1.
Enabled item can support Quad Data
Transfer interconnect to the VT8235
South Bridge.
58
SY-P4X400 DRAGON Lite
Item Help
Menu Level
ESC:Exit F1:General Help
F7: Optimized Defaults
Note
Default
Default
Default