Gated Mode; Output Type; Standard Waveforms; Arbitrary Waveforms - Racal Instruments 3151 User Manual

Gated Mode

Output Type

Standard
Waveforms

Arbitrary Waveforms

Sequenced
Waveforms
Getting Started 1-8
In gated mode, the Model 3151/3151A circuits are armed to generate
output waveforms as long as a gating signal is true. Unlike the
triggered mode, the gated mode is level sensitive. When the gating
signal goes false, the waveform at the output connector is first
completed and the output goes to an idle state. The stop amplitude
level, after a gating signal, is the last point on the waveform.
The Model 3151/3151A can output three types of waveforms:
standard waveforms, arbitrary waveforms and sequenced
waveforms. The three types of waveforms are described in the
following.
The Model 3151A generates waveforms from a memory that has to
be loaded before the instrument can generate waveforms. There are
512k points of memory. 1k points from this memory are allocated for
standard waveforms. Waveforms are loaded into this part of the
memory each time a standard function is selected.
The Model 3151/3151A can be programmed to output nine different
standard waveforms: sine wave, triangular wave, square wave,
pulse, ramp, sinc (sine(x)/x), pulse, gaussian pulse, exponential
pulse and DC. There are certain parameters that are associated with
each standard function. These parameters can be programmed to
generate modified standard waveforms.
The arbitrary waveform memory is capable of storing one or more
user waveforms. There are 523288 points that can be allocated to
one waveform that has this length. If there is no need to use the
complete memory, it can be divided into smaller segments, variable
in size. Load each segment with a different waveform and program
the Model 3151A to output the required waveform for a specific test.
Loading data to arbitrary waveform memory can be a time consuming
task, especially if the complete 512K is loaded in one shot. The
Model 3151A utilizes the VXIbus shared memory concept that
speeds data transfer from and to the host computer. In this mode,
the memory bank is disconnected from the CPU circuit and its bus is
accessible from the VXIbus for direct memory access by the host
computer.
The Model 3151/3151A employs a sophisticated circuit that allows
dividing the memory into smaller segments, linking of the segments
in user-defined order, and repeating of each linked segment up to
3151 And 3151A User Manual