Ic16 (Dsp Pcb): Cs5361-Ksr - Marantz SR7500/A1B Service Manual

IC16 (DSP PCB) : CS5361-KSR
RST 1
M/S 2
LRCK 3
4
SCLK
5
MCLK
6
VD
GND 7
VL 8
SDOUT 9
DIV 10
11
HPF
12
DIF
I/O
Pin Name #
RST I 1
M/S I 2
LRCK I 3
SCLK I 4
MCLK I 5
VD I 6
GND I 7,18
VL I 8
SDOUT O 9
DIV I 10
HPF I 11
DIF I 12
M0 I 13,
M1
I 14
TST I 15
AINL+ I 16,
AINL-
I 17
VA I 19
AINR+ I 20,
AINR-
I 21
VCOM O 22
REF_GND I 23
FILT+ O 24
24 FILT+
23 REFGND
F ILT +
22 VCOM
21
AINR+
A IN L-
20
AINR-
A IN L+
19
VA
18 GND
17 AINL-
16 AINL+
A IN R -
15 TST
A IN R +
14
M1
13
M0
Pin Description
Reset ( Input ) - The device enters a low power mode when low.
Master/Slave Mode (Input) -In Slave mode, LRCK and SCLK become input. (FIXED LOW)
Left Right Clock ( Input ) - Determines which channel, Left or Right, is currently active on the
serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
Serial Clock ( Input ) - Serial clock for the serial audio interface.
Master Clock ( Input ) - Clock source for the delta-sigma modulator and digital filters. Table 1 illustrates
several standard audio sample rates and the required master clock frequency.
Digital Power ( Input ) - Positive power supply for the digital section. Refer to the Recommended Operat-
ing Conditions for appropriate voltages.
Ground ( Input ) - Ground reference. Must be connected to analog ground.
Logic Power ( Input ) - Determines the required signal level for the digital input/output. Refer to the Rec-
ommended Operating Conditions for appropriate voltages.
Serial Audio Data Output ( Output ) - Output for two's complement serial audio data.
MCLK Divider (Input ) - (FIXED LOW)
High Pass Filter Enable (Input ) - The device includes a high pass filter after the decimator to remove
the indeterminate DC offsets introduced by the analog buffer stage and the analog modulator. The first-
order high pass filter response characteristics are detailed in the Digital Filter specifications table. The fil-
ter response scales linearly with sample rate.
Digital Interface Format ( Input ) - The required relationship between the Left/Right clock, serial clock
and serial data is defined by the Digital Interface Format selection. Refer to Figures 8 and 9.
Mode Selection ( Input ) -(FIXED LOW)
(FIXED LOW)
Test Pin (Input) - This pin needs to be connected to GND.
Differential Left Channel Analog Input ( Input ) - Signals are presented differentially to the delta-sigma
modulators via the AINL+/- pins. The full scale differential analog input level is specified in the Analog
Characteristics Specification table.
Analog Power ( Input ) - Positive power supply for the analog section. Refer to the Recommended Oper-
ating Conditions for appropriate voltages.
Differential Right Channel Analog Input ( Input ) -Signals are presented differentially to the delta-sigma
modulators via the AINR+/- pins. The full scale differential analog input level is specified in the Analog
Characteristics Specification table.
Common Mode Voltage (Output) - Nominally 2.5 volts; can be used to bias the analog input circuitry to
the common mode voltage of the CS5361. VCOM is not buffered and the maximum current is 10 uA.
Reference Ground ( Input ) - Ground reference for the internal sampling circuits and must be connected
to analog ground.
Positive Voltage Reference ( Output ) - Positive reference voltage for the internal sampling circuits.
Requires the capacitive decoupling to GND as shown in the Typical Connection Diagram.
V
V C O M
R E F G N D
L
Volta ge R e fe ren ce
+
LP Filter
Q
-
S /H
D A C
+
LP F ilter Q
-
S /H
D A C
76
S C L K
L R C K S D O U T M C LK
R S T
S e rial O utpu t Interfa ce
M /S
H ig h
D igital
D e cim ation P a ss
F ilter
F ilte r
H ig h
D igital
D e cim ation P a ss
F ilte r F ilter
D IF
H PF
D IV
M O D E 0
M O D E 1