Ic81 (Front Pcb): Nju3430Fg1 - Marantz SR7500/A1B Service Manual

IC81 (FRONT PCB) : NJU3430FG1
R S T
R ESET
Instruction
SI
CS 8bits
Shift
C L K
R e g .
R S
Timing
Gen.
OSC
1 C R
OSC .
OSC
2
V
D D
V
S S
V
F DP
N o . S Y M B O L
5 7 V
D D
4 9 V
S S
4 8 V
F D P
5 0 O S C
1
5 1 O S C
2
5 4 C L K
5 3 C S
5 5 S I
5 6 R S
5 2 R S T
6 1 t o 6 4 ,
S to S
1 3 5
1 t o 3 1
3 2 t o 4 7 T to T
1 1 6
6 0 M K
1
5 9 M K
2
5 8 P
1
D ec oder
Line
Address
Counter
State Address
Reg. Selector
Read
Display
Address
Control
Counter
I/O
- P o w e r S o u r c e
- G N D
V F D D r i v i n g P o w e r S o u r s e
-
V - 2 0 V t o V
D D
C R O s c i l l a t i o n T e r m i n a l
I
External R and C connect to these terminals.
(Target f = 3 6 0 k H z )
O S C
O
Serial Clock Input Terminal
I The serial data input synchronizing the rise edge of this
terminal.
C h i p S e l e c t T e r m i n a l
I W h e n t h e C S t e r m i n a l i s " H " t h e s e r i a l d a t a i n p u t i s n o t
a v a i l a b l e .
S e r i a l D a t a I n p u t T e r m i n a l
I
The data i np u t i s MSB fir st .
Register Selection Signal Input Terminal
I RS="0" : Instruction Register
R S = " 1 " : D a t a R e g i s t e r
R e s e t T e r m i n a l R S T = " L " : R e s e t
- E a c h A d d r e s s
- E a c h R A M D a t a
I
- D i s p l a y D i g i t s
- C o n t r a s t C o n t r o l
-All Display Off
-All Outputs are "L"
Segment Output Terminals (Internal Pull-down
O
R e s i s t a n c e )
O Timing Output Terminals (Internal Pull-down Resistance)
O Icon Output Terminals (Internal Pull-down Resistance)
Output Port Terminal
O
T h i s t e r m i n a l i s s u i t a b l e f o r L E D .
M K R AM
16x2 bit
C G R AM
35x8 bit
C G R O M
8,400bit
D D R A M
16x8 bit
F U N C T I O N
: V = + 3 . 0 t o 5 . 5 V
D D
: V = 0 V
S S
- 4 5 V
D D
: (00)
H
: Unfixed
: 1 6 - d i g i t
: 8/16 Dury
77
Icon
M K M K
~
1 2
D r i v e r
Segment
S S
~
1 35
D r i v e r
Port
P
1
D r i v e r
Timing
T T
~
D r i v e r 1 1 6