Marantz SR7500/A1B Service Manual page 55

IC19 (DSP PCB) : CS4900 Family
99 MCLK Audio Master Clock
100 VDD2 2.5V Supply Voltage
101 VSS2 2.5V Ground
102 I/O AUDATA4, Digital Audio Output 4, General Purpose I/O
GPIO28
103 I/O HDATA4, DSP C Bidirectional Data Bus, General Purpose I/O
GPIO4
104 O SCLK0 Audio Output Bit Clock
105 I/O HDATA3, DSP C Bidirectional Data Bus, General Purpose I/O
GPIO3
106 O AUDATA3, Digital Audio Output 3, S/PDIF Transmitter
XMT958A
107 O AUDATA2 Digital Audio Output 2
108 O LRCLK0 Audio Output Sample Rate Clock
109 O AUDATA1 Digital Audio Output 1
110 O AUDATA0 Digital Audio Output 0
111 I CMPCLK, PCM Audio Input Bit Clock
FSCLKN2
112 I/O HDATA2, DSP C Bidirectional Data Bus, General Purpose I/O
GPIO2
113 VSS3 2.5V Ground
114 VDD3 2.5V Supply Voltage
115 I/O HDATA1, DSP C Bidirectional Data Bus, General Purpose I/O
GPIO1
116 I/O HDATA0, DSP C Bidirectional Data Bus, General Purpose I/O
GPIO0
117 O CMPREQ, Frame Clock Data Request Out
FLRCLKN2
118 I CMPDAT, PCM Audio Data Input Number Two
FSDATAN2
119 I FLRCLKN1 PCM Audio Input Sample Rate Clock
120 I/O WR, DS, Host Write Strobe, Host Data Strobe, General Purpose I/O
GPIO10
121 I/O RD, R/W, Host Parallel Output Enable, Host Parallel R/W, General
GPIO11 Purpose I/O
122 PLLVSS PLL Ground Voltage
123 FILT2 Phase Locked Loop Filter
124 FILT1 Phase-Locked Loop Filter
125 PLLVDD PLL Supply Voltage
126 O CLKOUT, Crystal Oscillator Output
XTALO
127 I CLKIN, XTALI External Clock Input/Crystal Oscillator Input
128 CLKSEL DSP Clock Select
129 I/O CS, GPIO9 Host Parallel Chip Select, General Purpose I/O
130 I/O A0, GPIO13 Host Parallel Address Bit 0, General Purpose I/O
131 I FSDATAN1 PCM Audio Data Input One
132 VDD4 2.5V Supply Voltage
133 VSS4 2.5V Ground
134 I FSCLKN1, PCM Audio Input Bit Clock
STCCLK2
135 SCS Host Serial SPI Chip Select
136 I SCDIN SPI Serial Control Data Input
137 VSS5 2.5V Ground
138 VDD5 2.5V Supply Voltage
139 I/O A1, GPIO12 Host Address Bit 1, General Purpose I/O
140 I/O SCDOUT, Serial Control Port Data Input and Output
SCDIO
141 I/O HINBSY, Input Host Message Status, General Purpose I/O
GPIO8
142 SCCLK Serial Control Port Clock
143 I/O UHS2, Mode Select Bit 2, External Serial Memory Chip Select,
CS_OUT, General Purpose I/O
GPIO17
144 I RESET Master Reset Input
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