Aiwa CSD-A240 Service Manual page 21

Pin Name
Pin No.
39 RVSS
40 RCHO
41 RVDD
42 MUTER
43 XVDD
44 XOUT
45 XIN
46 XVSS
47 SBSY
48 EFLG
49 PW
50 SFSY
51 SBCK
52 FSX
53 WRQ
54 RWC
55 SQOUT
56 COIN
57 CQCK
58 RES
59 T11
60 16M
61 4.2M
62 T5
63 CS
64 T1
I/O
– Rch 1-bit DAC/Rch ground. Normally 0V.
O Rch output.
– Rch power supply.
O Rch muting output. (Not used)
– Power supply of crystal oscillator.
O
For the connection of a 16.93MHz crystal oscillator.
I
– Ground of crystal oscillator. Normally 0V.
O Subcode block sync signal output. (Not used)
O C1, C2, single, duplex correction monitor. (Not used)
O Output of subcodes P, Q, R, S, T, U and W. (Not used)
O Subcode frame sync signal output. Falls when the subcode is set to the standby state. (No used)
Subcode read-out clock input. Schmitt trigger input. ("L" is applied when not used.)
I
(Connected to 0V)
O 7.35kHz sync signal output obtained by dividing the oscillator frequency. (Not used)
O Subcode Q standby output.
I Read/write control input. Schmitt trigger input.
O Subcode Q output.
I Command input from the microprocessor.
Command input retrieval clock or subcode retrieval clock input from SQOUT. Schmitt trigger
I
input.
I LC78622NE reset input.
O Test output. Set to open (normally "L" output.) (Not used)
O 16.9344MHz output. (Not used)
O 4.236MHz output.
I Test input. A pull-down resistor is incorporated. (Connected to 0V)
I Chip select input. (Connected to 0V)
I Test input with no pull-down resistor. (Connected to 0V)
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Description