Sharp UX-B700 Service Manual page 66

UX-B700U
FO-B1600U
6) Sub scanning direction resolution conversion circuit
It reads 1 byte (8 dots in the main scanning direction) of data in the main
scan 600 dpi data buffer, converts the resolution in the sub scanning
direction, and stores the data in the sub scan 600 dpi data buffer. Then
it repeats this operation every 8 dots until reaching the end of line.
It further converts the data for 208 lines and sends out the completion
pulse when finished.
In the sub scanning direction, the input data per line may increase up to
13 lines and go over the swath. To simplify circuit configuration, apply
the same conversion method to after the 208th line and continue con-
version up to 220 lines. The lines 209th and over should be handled as
the next swath data.
7) Sub scan 600 dpi data buffer (buffer controller)
It performs pointer management to use the DRAM as a buffer for 440
lines (208 + 12 lines x 2).
The buffer cannot be cleared until swath data conversion (printing com-
mand output) is complete as it reads data in the line direction. To avoid
degraded performance, this buffer should have a capacity for 2 sets of
swath data. The buffer should store 220 lines per swath due to the con-
figuration of the sub scanning direction resolution conversion circuit.
8) Printing dot counting circuit/print duty judging circuit
It monitors the output data from the sub scanning direction resolution
conversion circuit and counts the number of black dots. When counting
of a swath (208 lines) is finished, it sends the result to the ESC com-
mand adding circuit to reflect it on the ESC command parameter.
To judge whether or not the print density of every inch (600 dots) in the
main scanning direction surpasses 50%, it counts the dots in 8 areas
(for 8 inches) every 75 bytes (600 dpi x 1 inch/8) after the line start. If the
print duty in any area surpasses 50%, the circuit notifies split printing to
the swath data conversion circuit. It further separates and counts odd-
and even-numbered slices in each area in order to clarify the number of
dots for split printing. When dots in all areas for a swath are counted,
odd- and even-numbered slices are totaled.
When the counting for a swath is finished, if both slices total 0, it notifies
the ESC command adding circuit to activate white skip operation and
clears the sub scan 600 dpi data buffer.
9) Swath data conversion circuit
This circuit reads data by 1-bit increments from the discrete address of
the sub scan 600 dpi data buffer and converts them into data of a slice.
When split printing is instructed from the printing dot calculation circuit,
it converts even-numbered slices for the first time. When conversion
completes, it creates odd-numbered slices without clearing the sub scan
600 dpi data buffer.
10) ESC command adding circuit
It adds a command line and a parameter to the printing data when a
print command is sent. Then sends a paper feed command for white
skip and a paper deliver command for after a single page printing.
11) IEEE1284 controller
It sends commands to, receives responses from and sends printing com-
mands and data to IEEE1284 interface of Hurricane.
12) Command buffer
It provides a buffer of 64 bytes to send commands from Fax Engine to
the printer (Hurricane). The actual buffer is located in the DRAM to keep
down the number of gates.
Therefore, equipped with a data path to the memory access arbiter and
an address controller to realize the buffer.
13) Response buffer
It provides a buffer of 1024 bytes to receive responses from the printer
(Hurricane) to Fax Engine. The actual buffer is located in the DRAM as
with the command buffer.
Also equipped with a data path to the memory access arbiter and an
address controller to realize the buffer.
14) FaxEngine bus interface
It functions as a bridge connecting the external bus of Fax Engine-LSI
and the internal bus of this ASIC. It operates at 1 wait except for the
accesses by the command or response buffer. As these two buffer ac-
cesses via the arbiter, the external wait will be generated by the RDY
signal.
15) Interruptive controller
It collects causes of interruption that occurs in the ASIC and generates
interruptive signals when interruption of Fax Engine firmware is prohib-
ited. It clears or retains interruption factors.
16) Memory access arbiter
It adjusts memory accesses from buffers. It possesses 9 access chan-
nels.
The arbitration logic needs to be devised in order to secure the data
transmission rate.
17) DRAM controller
It accesses memory using read cycle, early write cycle and CAS-before-
RAS refresh cycle of MSM51V4800E-70 [OKI] of 4Mbit Fast Page DRAM.
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