Kenwood TK-8102H Service Manual page 12

TK-8102H
PLL Frequency Synthesizer
The PLL circuit generates the first local oscillator signal
for reception and the RF signal for transmission.
PLL
The frequency step of the PLL circuit is 5 or 6.25kHz. A
16.8MHz reference oscillator signal is divided at IC1 by a
fixed counter to produce the 5 or 6.25kHz reference fre-
quency. The voltage controlled oscillator (VCO) output sig-
nal is buffer amplified by Q15, then divided in IC1 by a dual-
module programmable counter. The divided signal is com-
pared in phase with the 5 or 6.25kHz reference signal in the
phase comparator in IC1. The output signal from the phase
comparator is filtered through a low-pass filter and passed
to the VCO to control the oscillator frequency. (See Fig. 6)
VCO
The operating frequency is generated by Q11 in transmit
mode and Q10 in receive mode. The oscillator frequency is
controlled by applying the VCO control voltage, obtained
from the phase comparator, to the varactor diodes (D10 and
D12 in transmit mode and D9 and D11 in receive mode).
The TX/RX pin is set low in receive mode causing Q12 and
Q7 to turn Q11 off, and turn Q10 on. The TX/RX pin is set
high in transmit mode. The outputs from Q10 and Q11 are
amplified by Q15 and sent to the RF amplifiers.
IC1 : PLL IC
PLL
DATA
REF
OSC
16.8MHz
12
CIRCUIT DESCRIPTION
5kHz/6.25kHz
1/N
Phase Charge
comparator pump
1/M
5kHz/6.25kHz
Fig. 6 PLL circuit
Unlock Circuit
During reception, the 8RC signal goes high, the 8TC sig-
nal goes low, and Q29 turns on. Q31 turns on and a voltage
is applied to the collector (8R). During transmission, the
8RC signal goes low, the 8TC signal goes high and Q30
turns on. Q33 turns on and a voltage is applied to 8T.
The CPU in the control unit monitors the PLL (IC1) LD
signal directly. When the PLL is unlocked during transmis-
sion, the PLL LD signal goes low. The CPU detects this
signal and makes the 8TC signal low. When the 8TC signal
goes low, no voltage is applied to 8T, and no signal is trans-
mitted.
Q31
8R
SW
Q29
SW
8RC
Fig. 7 Unlock circuit
Q11
TX VCO
LPF
D10,12
Q10
RX VCO
D9,11
8C
Q33
8T
SW
Q30
SW
8TC
LD
IC6 IC1
CPU PLL
PLL lock
: LD "H"
Q3
AMP
Q15
BUFF
AMP
Q7,12
T/R SW