Chipset; Overview; I/O Hub (Ioh); Quickpath Interconnect (Qpi) - Dell PowerEdge M610 Technical Manual

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8 Chipset

8.1 Overview

The Dell™ PowerEdge™ M610 system board incorporates the Intel 5520 chipset for I/O and processor
interfacing. The chipset was designed to support the Intel
QuickPath Interconnect, and DDR3 memory technology. The chipset consists of the I/O Hub (IOH) and
Intel I/O Controller Hub 9 (ICH9).

8.2 I/O Hub (IOH)

The M610 system board uses the Intel 5520 chipset 24D IOH to provide a link between the
processor(s) and I/O components. The main components of the IOH consist of two full-width
QuickPath Interconnect links (one to each processor), 36 lanes of PCI Express Gen2, a x4 Direct Media
Interface (DMI), and an integrated IOxAPIC.
8.2.1

QuickPath Interconnect (QPI)

The QuickPath Interconnect architecture consists of serial point-to-point interconnects for the
processors and the IOH. The M610 has a total of three QuickPath Interconnect (QPI) links: one link
connecting the processors and links connecting both processors with the IOH. Each link consists of 20
lanes (full-width) in each direction with a link speed of 6.4 GT/s. An additional lane is reserved for a
forwarded clock. Data is sent over the QPI links as packets.
The QuickPath architecture implemented in the IOH and processors features four layers. The Physical
layer consists of the actual connection between components. It supports Polarity Inversion and Lane
Reversal for optimizing component placement and routing. The Link layer is responsible for flow
control and the reliable transmission of data. The Routing layer is responsible for the routing of QPI
data packets. Finally, the Protocol layer is responsible for high-level protocol communications,
including the implementation of a MESIF (Modify, Exclusive, Shared, Invalid, Forward) cache
coherence protocol.
8.2.2

IOH PCI Express

PCI Express is a serial point-to-point interconnect for I/O devices. PCIe Gen2 doubles the signaling
bit rate of Gen1 from 2.5 Gb/s to 5 Gb/s. Each of the PCIe Gen2 ports are backwards-compatible
with Gen1 transfer rates.
8.2.3

Direct Media Interface (DMI)

The DMI connects the IOH with the Intel I/O Controller Hub 9 (ICH9). The DMI is equivalent to a x4
PCIe Gen1 link with a transfer rate of 1 GB/s in each direction.

8.3 I/O Controller Hub 9 (ICH9)

ICH9 is a highly-integrated I/O controller, supporting the following functions:

Serial ATA (SATA) ports with transfer rates up to 300 MB/s

Six UHCI and two EHCI (high-speed 2.0) USB host controllers, with up to 12 USB ports ( M610
provides four of these ports for internal and external use)

Power management interface (ACPI 3.0b compliant)

Platform Environmental Control Interface (PECI)

I/O interrupt controller
Dell PowerEdge M610 Technical Guide
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Xeon Processor 5500 and 5600 series,
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