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Supports AMD Athlon XP/Athlon/Duron processors
Processor
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Supports 200/266 MHz Front-Side Bus
Note: Processors are automatically configured using
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Two 168-pin DIMM slots for SDRAM memory modules
Memory
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Two 184-pin DIMM slots for DDR memory modules
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Support SDRAM up to 133 MHz /DDR up to 266 MHz
memory bus
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Maximum installed memory is 1GB
Note: You cannot use SDRAM and DDR simultane-
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One AMR slot for a special audio/modem riser card
Expansion Slots
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One AGP4X slot for AGP 2.0-compliant interface
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Five 32-bit PCI slots for PCI 2.2-compliant bus interface
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Primary and Secondary PCI IDE channels
Onboard IDE
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Support for PIO (programmable input/output) modes
channels
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Support for Multiword DMA modes
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Support for Bus Mastering and Ultra DMA 33/66/100
modes
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ATX power supply connector
Power
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Meets ACPI 1.0b and APM 1.2 requirements, keyboard
Supply and
power on/off
Power
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Supports RTC Alarm, Wake On Modem, AC97 Wake-Up
Management
and USB Wake-Up
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Compliant AC97 2.2 specification
AC'97 Audio
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Supports 18-bit ADC (Analog Digital Converter) and DAC
Codec
(Digital Analog Converter) as well as 18-bit stereo full-
duplex codec
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Built-in 10BaseT/100BaseTX Ethernet LAN
Built-in Ethernet
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LAN controller integrates Fast Ethernet MAC and PHY
LAN (optional)
compliant with IEEE802.3u 100BASE-TX, 10BASE-T and
ANSI X3.263 TP-PMD standards
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Compliant with ACPI 1.0 and the Network Device Class
Power Management 1.0
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High Performance provided by 100Mbps clock generator
and data recovery circuit for 100Mbps receiver
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Built-in Multi-threaded IO Link Delivering 1.2GB/s
Onboard I/O
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Provides PC99 Color Connectors for easy peripheral
Ports
device connections
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Floppy disk drive connector with 1Mb/s transfer rate
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Two serial ports with 16550-compatible fast UART
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One parallel port with ECP and EPP support
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Two USB ports and optional two USB ports module
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Two PS/2 ports for keyboard and mouse
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One infrared port connector for optional module
Hardware Moni-
Built-in hardware monitoring for CPU & System temperatures,
toring
fan speeds and mainboard voltages.
firmware and a synchronous Host/DRAM Clock
Scheme.
ously.
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