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Circuit Description
When a carrier appears at the discriminator,
noise is removed from the output, causing pin 33
of Q1039 to go "high," in turn causing the "B
LED and audio output lines to turn on. The mi-
croprocessor then checks for CTCSS information.
If CTCSS decode is not activated, or if CTCSS de-
code is activated and a signal carrying a matching
tone is received, the microprocessor allows audio
to pass through AF mute gate Q1008 and audio
amplifier Q1003 to the speaker.
Transmit Signal Path
Speech input from the microphone is delivered
to the M
Unit, where it passes through the pre-
AIN
emphasis network (R1015 and C1031). The pre-
emphasized speech signal proceeds through the
AF high-pass filter at Q1009, then is applied to
the IDC (Instantaneous Deviation Control) at
Q1016-3 (NJM2902V), with deviation level being
set by potentiometer VR1001. The audio then pass-
es to a splatter filter in sections 1 and 4 of Q1016,
which filters out high-frequency components
which could result in over-deviation.
The processed audio is mixed with the CTCSS
tone (if activated) generated by CTCSS subsystem
IC Q1009, then delivered to D1041 (1SV276) for
frequency modulation of the PLL carrier (at the
transmitting frequency) up to ±5 kHz from the
unmodulated carrier frequency.
The modulated signal from the VCO, Q1046
(2SC5107), is buffered by Q1038 and Q1044 (both
2SC5107). The low-level transmit signal is then
amplified by Q1028 and Q1031 (both 2SC3357),
then applied to the final amplifier, Q1101
(M67741H), providing 25 Watts of transmitter
power. The transmit signal then passes through
the antenna switch, D1003/D1004 (both
UM9957F) and low-pass filter (which suppress-
es harmonic spurious radiation) before delivery
to the antenna jack.
16
Automatic Transmitter Power Control
RF output from the final amplifier is sampled
"
by C1039 and C1051 and rectified by D1005
USY
(1SS321). The resulting DC voltage is fed through
Automatic Power Controller Q1014 (2SB1143S),
Q1015 (2SC4116GR), and Q1017-2 to effect con-
trol of the gain of transmitter PA Q1011. The mi-
croprocessor, Q1039, issues commands for setting
"H
" or "L
IGH
OW
Transmit Inhibit
When the transmit PLL is unlocked, pin 2 of
PLL IC Q1050 (SC370651F) goes to logic "low"
level. The resulting DC unlock control voltage
switches off the T
which interrupts the supply voltage to the trans-
mitter PA, Q1011, thus disabling the transmitter.
Spurious Suppression
Generation of spurious products by the trans-
mitter is minimized by the fundamental carrier
frequency being equal to the final transmitting
frequency, modulated directly in the transmit
VCO. Additional harmonic suppression is pro-
vided by a low-pass filter consisting of L1001,
L1002, L1007, C1002, C1006, C1009, C1017,
C1019, C1036, and C1053, resulting in more than
60 dB of harmonic suppression prior to delivery
of the RF signal to the antenna jack.
PLL Frequency Synthesizer
The Phase-Locked Loop (PLL) circuitry on the
M
Unit includes VCO Q1046, VCO buffer
AIN
Q1044, and PLL subsystem IC Q1050, which in-
cludes a reference divider, serial-to-parallel data
latch, programmable divider, phase comparator,
and charge pump.
Stability of the reference oscillator, Q1047, is
maintained by a regulated 5 Volt supply, which
i n c l u d e s Q 1 0 0 1 ( M M 1 2 1 6 E N ) , Q 1 0 0 2
" power output.
inhibit switch Q1022 (IMZ1),
X
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