Transmit Inhibit - Vertex Standard VX-180U Service Manual

Circuit Description
Automatic Transmit Power Control
Current from the final amplifier is sampled by R1110,
R1124 and R1132, and is rectified by Q1033 (IMZ2A).
The resulting DC is fed back through Q1027 (FMW1) to
the drive amplifier Q1016 and final amplifier Q1021, for
control of the power output.
The microprocessor selects "High" or "Low" power
levels.

Transmit Inhibit

When the transmit PLL is unlocked, pin 14 of PLL
chip Q1004 goes to a logic "Low", and unlock detector
Q1054 (2SA1586Y) goes to a logic "High". The result-
ing DC unlock control voltage is passed to pin 14 of the
microprocessor Q1014. While the transmit PLL is un-
locked, pin 22 of Q1014 remains high, which then turns
off Q1031 (CPH6102) and the Automatic Power Con-
troller Q1027 (FMW1) to disable the supply voltage to
the drive amplifiers Q1012/Q1016 and final amplifier
Q1021, thereby disabling the transmitter.
Spurious Suppression
Generation of spurious products by the transmitter is
minimized by the fundamental carrier frequency being
equal to final transmitting frequency, modulated directly
in the transmit VCO. Additional harmonic suppression is
provided by a low-pass filter consisting of coils L1003,
L1006 and L1007 plus capacitors C1002, C1007, C1013,
C1017, C1022, C1029, C1169 and C1196, resulting in
more than 60 dB of harmonic suppression prior to deliv-
ery of the RF signal to the antenna.
PLL Frequency Synthesizer
The PLL circuitry on the Main Unit consists of VCO
Q1005 (2SK508-K52), VCO buffer Q1008 (2SC5005),
and PLL subsystem IC Q1004 (MB15A02PFV1), which
contains a reference divider, serial-to-parallel data latch,
programmable divider, phase comparator and charge pump.
Frequency stability is maintained by temperature com-
pensating thermistor TH1001. The output from TH1001
is applied to pin 39 of Q1014. Q1014 output thermal data
to D/A converter Q1052 (M62364FP) which produces a
DC voltage corresponding to the thermal data. The result-
ing DC voltage is applied to varactor diode D1004
(HVC350B) to stabilize the 14.60 MHz Reference Fre-
quency.
While receiving, VCO Q1005 oscillates between
405.75 and 440.75 MHz according to the transceiver ver-
sion and the programmed receiving frequency. The VCO
output is buffered by Q1008, then applied to the prescaler
section of Q1004. There the VCO signal is divided by 64
or 65, according to a control signal from the data latch
section of Q1004, before being sent to the programmable
divider section of Q1004.
12
The data latch section of Q1004 also receives serial
dividing data from the microprocessor Q1014, which
causes the pre-divided VCO signal to be further divided
in the programmable divider section, depending upon the
desired receive frequency, so as to produce a 5 kHz or
6.25 kHz derivative of the current VCO frequency.
Meanwhile, the reference divider section of Q1005
divides the 14.60 MHz crystal reference from the refer-
ence oscillator Q1022, by 2920 (or 2336) to produce the 5
kHz (or 6.25 kHz) loop references (respectively).
The 5 kHz (or 6.25 kHz) signal from the programmable
divider (derived from the VCO) and that derived from the
reference oscillator are applied to the phase detector sec-
tion of Q1004, which produces a pulsed output with pulse
duration depending on the phase difference between the
input signals.
This pulse train is filtered to DC and returned to
varactors D1001 (HVC355B) and D1002 (HVC355B).
Changes in the level of the DC voltage are applied to the
varactors, affecting the reference in the tank circuit of the
VCO according to the phase difference between the sig-
nals derived from the VCO and the crystal reference os-
cillator.
The VCO is thus phase-locked to the crystal reference
oscillator. The output of the VCO Q1005, after buffering
by Q1008, is applied to the first mixer as described previ-
ously.
For transmission, the VCO Q1005 oscillates between
450 and 485 MHz according to the model version and
programmed transmit frequency. The remainder of the PLL
circuitry is shared with the receiver. However, the divid-
ing data from the microprocessor is such that the VCO
frequency is at the actual transmit frequency (rather than
offset for IFs, as in the receiving case). Also, the VCO is
modulated by the speech audio applied to D1005
(HVC350B), as described previously.
Receive and transmit buses select which VCO is made
active, using Q1002 (RT1N441U).
Miscellaneous Circuits
Push-To-Talk Transmit Activation
The PTT switch on the microphone is connected to pin
48 of microprocessor Q1014, so that when the PTT switch
is closed, pin 23 of Q1014 goes low. This signal disables
the receiver by disabling the 5 V supply bus at Q1035
(DTB123EK) to the front-end, FM IF subsystem IC
Q1036 and the receiver VCO circuitry.
At the same time, Q1026 (FMW1) and Q1031
(CPH6102) activate the transmit 5V supply line to en-
able the transmitter.