Abit IT5 Series User Manual page 91

Intel Pentium CPUs
Y Bus Factor
Power STD
VR
VRE 3.450V~3.6V (Recommended voltage is 3.52V)
Timing STD
MD
Kit
P54C
1. Beginning with the P54C E -Step, standard timings have been replaced by
existing Min Delay timing
P54CS
1. P54CS PPGA UP:No DP,No APIC,No FRC
2. Beginning with the P54C E-Step, standard timings have been replaced by
existing Min Delay timing.
P55C
1. P55C A-Step is NOT production stepping
2. A-1 step:
3. A-2 Step and B step: Vcc and timing on production stepping i s 2.8V +/-
0.1V
3.15V~3.465V (Recommended voltage is 3.38V)
3.300V~3.465V (Recommended voltage is 3.38V)
Standard Timing
Min. Delay (denoting shorter minimum valid delay AC timing
for some signal)
Supports timing for C55/C88 cache chipsets & design
.
Vcc and timing on initial samples is 2.9V +/- 0.1V
B-7