IBM DBCA-204860 - Travelstar 4.8 GB Hard Drive Specifications
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IBM DBCA-204860 - Travelstar 4.8 GB Hard Drive Specifications

IBM DBCA-204860 - Travelstar 4.8 GB Hard Drive Specifications

( 3.2 / 4.8 / 6.4 gb ) 2.5-inch hard disk drive with ata interface
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S25L-2426-02
OEM HARD DISK DRIVE SPECIFICATIONS
for
DBCA-203240/204860/206480 ( 3.2 / 4.8 / 6.4 GB )
2.5-Inch Hard Disk Drive with ATA Interface
Revision (1.0)

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Summary of Contents for IBM DBCA-204860 - Travelstar 4.8 GB Hard Drive

  • Page 1 S25L-2426-02 OEM HARD DISK DRIVE SPECIFICATIONS DBCA-203240/204860/206480 ( 3.2 / 4.8 / 6.4 GB ) 2.5-Inch Hard Disk Drive with ATA Interface Revision (1.0)
  • Page 3 S25L-2426-02 OEM HARD DISK DRIVE SPECIFICATIONS DBCA-203240/204860/206480 ( 3.2 / 4.8 / 6.4 GB ) 2.5-Inch Hard Disk Drive with ATA Interface Revision (1.0)
  • Page 4 This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information herein; these changes will be incorporated in new editions of the publication. IBM may make improvements and/or changes in the product(s) and/or the program(s) described in this publication at any time.

  • Page 5: Table Of Contents

    ......... Copyright IBM Corp. 1998...
  • Page 6 5.5 Vibration and Shock ..........5.5.1 Operating Vibration .
  • Page 7 9.10 Features Register ..........9.11 Sector Count Register .
  • Page 8 12.1 Check Power Mode (E5h/98h) ........12.2 Execute Device Diagnostic (90h) .

  • Page 9: General

    1.0 General This document describes the specifications of the following IBM 2.5-inch, ATA interface hard disk drives: DBCA-203240 (3250 MB) DBCA-204860 (4870 MB) DBCA-206480 (6490 MB) Note: The specifications are subject to change without notice. 1.1 Glossary Word Meaning Kbpi...

  • Page 10: Caution Of Usage

    1.2.1 Caution of usage Figure 1. Handling caution of DBCA-203240/204860/206480 O E M Specifications of DBCA-2xxxxx 2.5 inch H D D...
  • Page 11 Figure 2. Breathing hole caution of DBCA-203240/204860/206480 General...
  • Page 12 O E M Specifications of DBCA-2xxxxx 2.5 inch H D D...

  • Page 13: General Features

    Adaptive power save control (0.65 Watt at low-power idle state) 2.8 sec Power on to ready Shock Non-operation : 700G/1ms Operation : 150G/2ms Address Offset Feature to support D F T implementation Note: Mounting screw position is Incompatible with DBOA/DMCA/DCRA/DSOA/DPRA-2xxxx. Compatible with DTNA/DLGA/DDLA/DTCA/DPLA/DYKA/DYLA/DADA/ DKLA/DCYA/DCXA-2xxxxx. Copyright IBM Corp. 1998...
  • Page 14 O E M Specifications of DBCA-2xxxxx 2.5 inch H D D...

  • Page 15: Part 1. Functional Specification

    Part 1. Functional Specification Copyright IBM Corp. 1998...
  • Page 16 O E M Specifications of DBCA-2xxxxx 2.5 inch H D D...

  • Page 17: Drive Characteristics

    286.1 Maximum Track density [ TPI] 19,900 Areal density [ Gb/sq.in.] 5.7 Maximum Number of zone Number of disks 1 / 2 Number of heads 2 / 3 / 4 Servo design method Embedded sector servo Copyright IBM Corp. 1998...

  • Page 18: Performance Characteristics

    3.3 Performance Characteristics File performance is characterized by the following parameters: Command Overhead Mechanical Positioning Seek Time Latency Data Transfer Speed Buffering Operation Note: All the above parameters contribute to a file performance. There are other parameters which con- tribute to the performance on the actual system. This specification tries to define the essential file character- istics, not the system throughput which is dependent on the system and the application.

  • Page 19: Single Track Seek Time

    The seek time is measured from the start of motion of the actuator to the start of a reliable read or write operation. Reliable read or write implies that error correction/recovery is not employed to correct for arrival problems. The Average Seek Time is measured as the weighted average of all possible seek combinations. m a x S U M ( m a x + 1 n ) ( T n .

  • Page 20: Drive Ready Time

    3.3.6 Drive Ready Time Condition Typical Power On To Ready 2.8 sec 9.5 sec Figure 10. Drive Ready Time Ready The condition in which the drive is able to perform a media access command (e.g. read, write) immediately. Power On This includes the time required for the internal self diagnostics.

  • Page 21: Operating Modes

    3.3.7 Operating Modes. O p e r a t i n g m o d e D e s c r i p t i o n S p i n U p S t a r t u p t i m e p e r i o d f r o m s p i n d l e s t o p o r p o w e r d o w n . S e e k S e e k o p e r a t i o n m o d e W r i t e...

  • Page 22: Mode Transition Time

    3.3.7.1 Mode Transition Time. F r o m T r a n s i t i o n T i m e S t a n d b y I d l e 1 . 8 s e c t y p , 9 .

  • Page 23: Data Integrity

    Appropriate error status is made available to the host system if any of the following conditions occur after the drive has once become ready: Spindle speed outside requirements for reliable operation. Occurrence of a Write Fault condition. Copyright IBM Corp. 1998...

  • Page 24: Write Safety

    4.4 WRITE Safety The drive ensures that the data is written into the disk media properly. Following conditions are monitored during a write operation. When one of those conditions exceeds the criteria, the write operation is terminated and automatic retry sequence will be invoked. Head off track External shock Low supply voltage...

  • Page 25: Specification

    The system has to provide sufficient ventilation to maintain a surface temperature below 60 ˚ C at the center of the top cover of the drive. Non-condensing should be kept at any time. Maximum storage period with shipping package is one year. Figure 14. Limits of Temperature and Humidity Copyright IBM Corp. 1998...

  • Page 26: Magnetic Fields

    5.1.2 Magnetic Fields The disk drive will withstand radiation & conductive noise within the limits shown below. 5.1.2.1 Radiation Noise The disk drive shall work without degradation of the soft error rate under the following Magnetic Flux Density Limits at the enclosure surface. Frequency ( KHz ) Limits ( Gauss rms ) 0 - 60...

  • Page 27: Dc Power Requirements

    5.2 DC Power Requirements Connection to the product should be made in isolated secondary circuits (SELV). The voltage specifications are applied at the power connector of the drive. Item Requirements Notes Nominal Supply + 5 Volt Power Supply Ripple ( 0- 20Mhz) 100 mv p-p max Tolerance + / - 5 %...

  • Page 28: Start Up Current

    5.2.1 Start Up Current Figure 17. Typical current wave form at start up. O E M Specifications of DBCA-2xxxxx 2.5 inch H D D...

  • Page 29: Reliability

    Service life of DBCA-2xxxxx is approximately 5 years or 15,000 power-on hours, whichever comes first. Actual product life and failure rate depend on duty cycle and environmental conditions. Consult your IBM representative for reliability estimate if atypical operating conditions are anticipated. 5.3.5 Preventive Maintenance None.

  • Page 30: Load/Unload

    5.3.6 Load/Unload The product supports a minimum of 300,000 normal load/unloads. Load/unload is a functional mechanism of the HDD. It is controlled by the drive microcode. Specifically, unloading of the heads is invoked by the commands: Soft Reset Standby Standby Immediate Sleep Load/unload is also invoked as one of the idle modes of the drive.
  • Page 31 DBCA-2xxxxx invokes the emergency unload mechanism, and subjects the H D D to non- typical mechanical stress. Power cycling testing may be required to test the boot-up function of the system. In this case IBM recom- mends that the power-off portion of the cycle contain the sequence specified in 5.3.6.2, “ Required Power-Off Sequence”...

  • Page 32: Mechanical Specifications

    5.4 Mechanical Specifications 5.4.1 Mechanical Dimensions and Weight The following chart describes the dimensions for the 2.5" hard disk drive form factor. DBCA-203240 / DBCA-204860 / DBCA-206480 Height (mm) 9.5 ± 0.2 Width (mm) 69.85 ± 0.25 Length (mm) 100.2 ± 0.25 Weight (gram) 99 Typical (101 Max) Figure 18.

  • Page 33: Mounting Orientation

    5.4.3 Mounting Orientation The drive will operate in all axes (6 directions). The drive will operate within the specified error rates when tilted ± 5 degree from these positions. Performance and error rate will stay within specification limits if the drive is operated in the other permis- sible orientations from which it was formatted.

  • Page 34: Vibration And Shock

    5.5 Vibration and Shock All vibration and shock measurements in this section shall be for the disk drive without the mounting attach- ments for the systems. The input level shall be applied to the normal drive mounting points. Vibration test and shock test are to be conducted by mounting the drive to the table using the bottom four screws.

  • Page 35: Operating Shock

    5.5.2.2 Swept Sine Vibration 25.4mm (peak to peak) displacement, 5 to 10 to 5 Hz 5 G (zero to peak), 10 to 500 to 10 Hz sine wave 0.5 oct/min sweep rate 5.5.3 Operating Shock The hard disk drive meets the following criteria while operating in the conditions described below. The shock test consists of ten shock inputs in each axis and direction for a total of 60.

  • Page 36: Acoustics

    5.6 Acoustics 5.6.1 Sound Power Level The criteria of A-weighted sound power level is described below. Measurements are to be taken in accordance with ISO 7779. The mean of 40 drives is to be less than the typical value. Each drive is to be less than the maximum value. Drives are to meet this requirement in both board down orientations.

  • Page 37: Discrete Tone Penalty

    5.6.2 Discrete Tone Penalty Discrete tone penalties are added to the A-weighted sound power (Lw) with following formula only when determining compliance. Lwt(spec)=Lw+0.1*Pt+0.3 < 4.0 (Bels) where: : A-weighted sound power level. : Value of discrete tone penalty = dLt-6.0 (dBA) : Tone-to-noise ratio taken in accordance with ISO 7779.

  • Page 38: Identification

    5.7.1 Labels The following labels are affixed to every disk drive . A label placed on the top of the HDA containing the statement 'Made by IBM' or equivalent, Part No., EC No. and F R U No. A bar code label placed on the disk drive based on user request. The location on the disk drive is to be designated in the drawing.

  • Page 39: Safety

    5.9 Safety 5.9.1 Underwriters Lab(UL) Approval DBCA-2xxxxx complies with UL 1950:1995+A1. 5.9.2 Canadian Standards Authority(CSA) Approval DBCA-2xxxxx complies with CSA C22.2 950-M1995. 5.9.3 IEC Compliance DBCA-2xxxxx complies with IEC 950:1991+A1-4. 5.9.4 German Safety Mark DBCA-2xxxxx are approved by TUV on Test Requirement: EN 60 950:1992+A1-4.
  • Page 40 O E M Specifications of DBCA-2xxxxx 2.5 inch H D D...

  • Page 41: Electrical Interface Specifications

    Figure 21. AT Attachment connector of DBCA-2xxxxx Note 1 : Pin position 20 is left blank for correct connector insertion. Note 2 : Pin position A,B,C,D are used for drive address setting. (Refer to Figure 36 on page 50 for address setting.) Copyright IBM Corp. 1998...

  • Page 42: Signal Definition

    6.2.1 Signal Definition The pin assignments of interface signals are listed as follows: P I N S I G N A L I / O T y p e P I N S I G N A L I / O T y p e R E S E T T T L...
  • Page 43 7. "(Resv)" designates reserved pin which must be left unconnected. DD00-DD15 16-bit bi-directional data bus between the host and the HDD. The lower 8 lines, DD00-07, are used for Register and ECC access. All 16 lines, DD00-15, are used for data transfer. These are 3-State lines with 24 mA current sink capability.
  • Page 44 00h. Device 0 may be unable to accept commands until it has finished its reset procedure and is ready ( D R D Y = 1 ) . CSEL (Cable Select) This signal is monitored to determine the drive address, 0 or 1, when the jumper on the interface connector is at Position-3.

  • Page 45: Interface Logic Signal Levels

    STOP (Ultra DMA) This signal is used only for Ultra D M A data transfers between host and drive. STOP shall be asserted by the host prior to initiation of an Ultra D M A burst. STOP shall be negated by the host before data is transferred in an Ultra D M A burst. Assertion of STOP by the host during or after data transfer in an Ultra D M A mode signals the termination of the burst.

  • Page 46: Reset Timings

    6.4 Reset timings H D D reset timing. R E S E T < > B U S Y X X X X X X X < > P A R A M E T E R D E S C R I P T I O N M i n M a x ( u s e c )

  • Page 47: Pio Timings

    6.5 PIO Timings The PIO cycle timings meet Mode 4 of the ATA-3 description. C S 0 , C S 1 + D A 0 2 < > < T 1 > < > D I O R , D I O W <...

  • Page 48: Dma Timings (Single Word)

    6.5.1 DMA Timings (Single Word) The Single Word D M A timing meets Mode 2 of the ATA-3 description. + D M A R Q < > < > : D M A C K > T I < > T J < D I O R / D I O W <...

  • Page 49: Dma Timings (Multiword)

    6.5.2 DMA Timings (Multiword) The Multiword D M A timing meets Mode 2 of the ATA-3 description. + D M A R Q < T L > D M A C K < > > T J < > T I < >...

  • Page 50: Ultra Dma Timings

    6.5.3 Ultra DMA Timings The Ultra D M A timing meets Mode 0, 1 and 2 of the Ultra DMA/33 -- a Proposal for a New Protocol in ATA/ATAPI-4 (X3T13/D96153 Revision 1) 6.5.3.1 Initiating Read DMA D M A R Q <...

  • Page 51: Host Pausing Read Dma

    6.5.3.2 Host Pausing Read DMA D M A R Q D M A C K S T O P < T s r > H D M A R D Y < T r f s > D S T R O B E [ n s e c ] M O D E 0 M O D E 1...

  • Page 52: Host Terminating Read Dma

    6.5.3.3 Host Terminating Read DMA < T l i > D M A R Q < T m l i > D M A C K < T r p > < T a c k > S T O P <...

  • Page 53: Device Terminating Read Dma

    6.5.3.4 Device Terminating Read DMA < > T s s D M A R Q < T m l i > D M A C K < T l i > < T a c k > S T O P <...

  • Page 54: Initiating Write Dma

    6.5.3.5 Initiating Write DMA D M A R Q < T u i > D M A C K < T a c k > < T e n v > S T O P T z r d y > <...

  • Page 55: Device Pausing Write Dma

    6.5.3.6 Device Pausing Write DMA D M A R Q D M A C K S T O P < T s r > D D M A R D Y < T r f s > H S T R O B E [ n s e c ] M O D E 0 M O D E 1...

  • Page 56: Device Terminating Write Dma

    6.5.3.7 Device Terminating Write DMA < T r p > D M A R Q < T m l i > D M A C K < T a c k > S T O P < > T r d y z D D M A R D Y <...

  • Page 57: Host Terminating Write Dma

    6.5.3.8 Host Terminating Write DMA < T l i > D M A R Q < T m l i > D M A C K < > T s s < T a c k > S T O P <...

  • Page 58: Drive Address Setting

    6.6 Drive Address Setting A jumper is available at the interface connector to determine the drive address. The set position of the jumper is as shown in Figure 36. Using Cable Selection, the drive address depends on the condition of pin 28 of the AT interface cable. In the case when pin 28 is ground or low, the drive is a Master.

  • Page 59: Addressing Of Drive Registers

    The -HCS0 is used to address Command Block registers. while the -HCS1 is used to address Control Block registers. The following table shows the standard I/O address range for IBM PC-AT machines. A d d r . C S 0...
  • Page 60 O E M Specifications of DBCA-2xxxxx 2.5 inch H D D...

  • Page 61: Part 2. Ata Interface Specification

    Part 2. ATA Interface Specification Copyright IBM Corp. 1998...
  • Page 62 O E M Specifications of DBCA-2xxxxx 2.5 inch H D D...

  • Page 63: General

    Host indicates the system that the device is attached to. First Command The command which is executed first right after power on reset or hard reset when the initial power mode at power on is Standby mode. INTRQ Interrupt request (Device or Host) Copyright IBM Corp. 1998...
  • Page 64 O E M Specifications of DBCA-2xxxxx 2.5 inch H D D...

  • Page 65: Deviations From Standard

    Count register value) x 5 seconds. Check Power Mode While the drive is in idle mode, F F h is returned as a response to Check Power Mode command. 80h is not used for the response. Copyright IBM Corp. 1998...
  • Page 66 O E M Specifications of DBCA-2xxxxx 2.5 inch H D D...

  • Page 67: Registers

    (CS0-, CS1-, DA2, DA1, DA0, DIOR- and DIOW-). The Command Block Registers are used for sending commands to the device or posting status from the device. The Control Block Registers are used for device control and to post alternate status. Copyright IBM Corp. 1998...

  • Page 68: Alternate Status Register

    9.1 Alternate Status Register A l t e r n a t e S t a t u s R e g i s t e r B S Y R D Y D S C D R Q C O R I D X E R R Figure 39.

  • Page 69: Data Register

    9.5 Data Register This register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format Track command, and configuration information is transferred on an Identify Device command. All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide.

  • Page 70: Device/Head Register

    -DS1 -Drive Select 1. Drive select bit for device 1, active low. D S 1 = 0 when device 1 (slave) is selected and active. -DS0 -Drive Select 0. Drive select bit for device 0, active low. D S 0 = 0 when device 0 (master) is selected and active.

  • Page 71: Features Register

    Bit Definitions ICRCE (CRC) Interface C R C Error. C R C = 1 indicates a C R C error has occurred on the data bus during a Ultra-DMA transfer. Uncorrectable Data Error. U N C = 1 indicates an uncorrectable data error has been encountered.
  • Page 72 This register contains the device status. The contents of this register are updated whenever an error occurs and at the completion of each command. If the host reads this register when an interrupt is pending, it is considered to be the interrupt acknowledge. Any pending interrupt is cleared whenever this register is read.

  • Page 73: General Operation Descriptions

    SRST bit in the Device Control Register is set, then is reset. The device resets the interface circuitry according to the Set Features requirement. The actions of each reset is shown in Figure 45 on page 66. Copyright IBM Corp. 1998...
  • Page 74 P O R h a r d s o f t r e s e t r e s e t A b o r t i n g H o s t i n t e r f a c e A b o r t i n g D e v i c e o p e r a t i o n ( * 1 ) ( * 1 )

  • Page 75: Register Initialization

    10.1.1 Register Initialization R e g i s t e r D e f a u l t V a l u e E r r o r D i a g n o s t i c C o d e S e c t o r C o u n t 0 1 h S e c t o r N u m b e r...

  • Page 76: Diagnostic And Reset Considerations

    10.2 Diagnostic and Reset considerations For each Reset and Execute Device Diagnostic, the diagnostic is done as follows: Power On Reset, Hard Reset DASP- is read by Device 0 to determine if Device 1 is present. If Device 1 is present Device 0 shall read PDIAG- to determine when it is valid to clear the BSY bit and whether Device 1 has powered on or reset without error, otherwise Device 0 clears the BSY bit whenever it is ready to accept commands.

  • Page 77: Sector Addressing Mode

    10.3 Sector Addressing Mode All addressing of data sectors recorded on the device's media is by a logical sector address. The logical CHS address for DBCA-2xxxxx is different from the actual physical CHS location of the data sector on the disk media.

  • Page 78: Power Management Feature

    10.4 Power Management Feature The power management feature set permits a host to modify the behavior in a manner which reduces the power required to operate. The power management feature set provides a set of commands and a timer that enables a device to implement low power consumption modes.

  • Page 79: Standby Timer

    5. Activate the spindle break to stop the spindle motor 6. Wait until spindle motor is stopped 7. Perform post process 10.4.4 Standby timer The standby timer provides a method for the device to automatically enter standby mode from either active or idle mode following a host programmed period of inactivity.

  • Page 80: Advanced Power Management Feature (Able-3)

    10.5 Advanced Power Management Feature (ABLE-3) This feature provides power saving without performance degradation. The Adaptive Battery Life Extender 3 (ABLE-3) technology intelligently manages transition among power modes within the device by monitoring access patterns of the host. This technology has three idle modes; Performance Idle mode, Active Idle mode, and Low Power Idle mode. This feature allows the host to select an advanced power management level.
  • Page 81 transition time with the condition that the calculated response delay is shorter than the value calculated from the specifid level by Set Feature Enable Adaptive Power Management command. The optimal time to enter Active Idle mode is variable depending on the users recent behavior. It is not possible to achieve the same level of Power savings with a fixed entry time into Active Idle because every users data and access pattern is different.

  • Page 82: Function

    10.6 S.M.A.R.T. Function The intent of Self-monitoring, analysis and reporting technology (S.M.A.R.T) is to protect user data and prevent unscheduled system downtime that may be caused by predictable degradation and/or fault of the device. By monitoring and storing critical performance and calibration parameters, S.M.A.R.T devices employ sophisticated data analysis algorithms to predict the likelihood of near-term degradation or fault con- dition.

  • Page 83: Operation With Power Management Modes

    10.6.6 S.M.A.R.T. operation with power management modes It is recommended that, when a host system utilizes both the power management and S.M.A.R.T. features, the system enable the device's attribute autosave feature to allow the device's automatic attribute saving upon receipt of STANDBY IMMEDIATE or SLEEP commands. If the device has been set to utilize the standby timer, the devce also saves attributes values prior to going from an Idle state to Standby state.

  • Page 84: Security Mode Feature Set

    10.7 Security Mode Feature Set Security Mode Feature Set is a powerful security feature. With a device lock password, a user can prevent unauthorized access to hard disk device even if the device is removed from the computer. New commands are supported for this feature as below. Security Set Password ('F1'h) Security Unlock...

  • Page 85: Operation Example

    The system manufacturer/dealer who intends to enable the device lock function for the end users, must set the master password even if only single level password protection is required. 10.7.4 Operation example 10.7.4.1 Master Password setting The system manufacturer/dealer can set a new Master Password from default Master Password using the Security Set Password command, without enabling the Device Lock Function.
  • Page 86 10.7.4.3 Operation from POR after User Password is set When Device Lock Function is enabled, the device rejects media access command until a Security Unlock command is successfully completed. P O R > D e v i c e L o c k e d m o d e <...

  • Page 87: User Password Lost

    10.7.4.4 User Password Lost If the User Password is forgotten and High level security is set, the system user can't access any data. However the device can be unlocked using the Master Password. If a system user forgets the User Password and Maximum security level is set, data access is impossible. However the device can be unlocked using the Security Erase Unit command to unlock the device and erase all user data with the Master Password.

  • Page 88: Command Table

    10.7.5 Command Table This table shows the device's response to commands when the Security Mode Feature Set (Device lock func- tion) is enabled. D e v i c e D e v i c e D e v i c e C o m m a n d L o c k e d U n l o c k F r o z e n M o d e...
  • Page 89 D e v i c e D e v i c e D e v i c e C o m m a n d L o c k e d U n l o c k F r o z e n M o d e M o d e M o d e...

  • Page 90: Protected Area Function

    10.8 Protected Area Function Protected Area Function is to provide the 'protected area' which can not be accessed via conventional method. This 'protected area' is used to contain critical system data such as BIOS or system management information. The contents of entire system main memory may also be dumped into 'protected area' to resume after system power off.
  • Page 91 3. Conventional usage without system software support Since the H D D works as 528MB device, there is no special care to use this device for normal use. 4. Advanced usage using protected area The data in the protected area is accessed by following. Issue Read Native Max Address command to get the real device max LBA/CYL.

  • Page 92: Address Offset Feature (Vendor Specific)

    10.9 Address Offset Feature (Vendor Specific) Computer systems perform initial code loading (booting) by reading from a predefined address on a disk drive. To allow an alternate bootable operating system to exist in a reserved area on a disk drive this feature provides a Set Features function to temporarily offset the drive address space.

  • Page 93: Identify Device Data

    B e f o r e E n a b l e A d d r e s s O f f s e t M o d e A r e s e r v e d a r e a h a s b e e n c r e a t e d u s i n g a n o n v o l a t i l e S e t M a x c o m m a n d . U s e r A c c e s s i b l e A r e a R e s e r v e d A r e a L B A 0...

  • Page 94: Write Cache Function

    10.10 Write Cache Function Write cache is a performance enhancement whereby the device reports completion of the write command (Write Sectors and Write Multiple) to the host as soon as the device has received all of the data into its buffer.

  • Page 95: Reassign Function

    The conditions for auto-reallocation are described below. When a device shipped from IBM, a minimum of 791 usable spare sectors are available. Non recovered write errors When a write operation can not be completed after the Error Recovery Procedure(ERP) is fully carried out, the sector(s) are reallocated to the spare location.
  • Page 96 O E M Specifications of DBCA-2xxxxx 2.5 inch H D D...

  • Page 97: Command Protocol

    In response to the interrupt, the host reads the Status Register. d. The device clears the interrupt in response to the Status Register being read. e. The host reads one sector (or block) of data via the Data Register. Copyright IBM Corp. 1998...

  • Page 98: Data Out Commands

    f. The device sets D R Q = 0 after the sector (or block)has been transferred to the host. 4. For the Read Long command: a. The device sets B S Y = 1 and prepares for data transfer. b. When the sector of data is available for transfer to the host, the device sets B S Y = 0 , sets D R Q = 1 , and interrupts the host.
  • Page 99 Write Sectors Write Verify Execution includes the transfer of one or more 512 byte ( > 5 1 2 bytes on Write Long) sectors of data from the host to the device. 1. The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head Registers.

  • Page 100: Non-Data Commands

    11.3 Non-Data Commands These commands are: Check Power Mode Execute Device Diagnostic Flush Cache Format Unit Idle Idle Immediate Initialize Device Parameters Read Native Max Address Read Verify Sectors Recalibrate Security Erase Prepare Security Freeze Lock Seek Set Features Set Max Address Set Multiple Mode Sleep SMART Disable Operations...

  • Page 101: Dma Data Transfer Commands

    11.4 DMA Data Transfer Commands These commands are: Identify Device D M A Read D M A Write D M A Data transfer using D M A commands differ in two ways from PIO transfers: data transfers are performed using the slave-DMA channel no intermediate sector interrupts are issued on multi-sector commands Initiation of the D M A transfer commands is identical to the Read Sector or Write Sector commands except that the host initializes the slave-DMA channel prior to issuing the command.
  • Page 102 O E M Specifications of DBCA-2xxxxx 2.5 inch H D D...

  • Page 103: Command Descriptions

    1 1 1 1 1 0 0 1 S e t M u l t i p l e M o d e 1 1 0 0 0 1 1 0 Figure 56. Command Set -- continued -- Copyright IBM Corp. 1998...
  • Page 104 P r o t o C o m m a n d C o d e B i n a r y C o d e c o l ( H e x ) B i t 7 6 5 4 3 2 1 0 S l e e p 1 1 1 0 0 1 1 0 S l e e p *...
  • Page 105 C o m m a n d F e a t u r e C o m m a n d ( S u b c o m m a n d ) C o d e R e g i s t e r ( H e x ) ( H e x ) ( S .
  • Page 106 The following symbols are used in the command descriptions: Output Registers Indicates that the bit must be set to 0. Indicates that the bit must be set to 1. The device number bit. Indicates that the device number bit of the Device/Head Register should be specified.

  • Page 107: Check Power Mode (E5H/98H)

    12.1 Check Power Mode (E5h/98h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 108: Execute Device Diagnostic (90H)

    12.2 Execute Device Diagnostic (90h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 109: Flush Cache (E7H)

    12.3 Flush Cache (E7h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 110: Format Track (50H: Vendor Specific)

    12.4 Format Track (50h: Vendor Specific) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 111 Input Parameters From The Device Sector Number In LBA mode, this register specifies current LBA address bits 0-7. ( L = 1 ) Cylinder High/Low In LBA mode, this register specifies current LBA address bits 8 - 15 (Low), 16 - 23 (High) In LBA mode, this register specifies current LBA address bits 24 - 27.

  • Page 112: Format Unit (F7H: Vendor Specific)

    12.5 Format Unit (F7h: Vendor Specific) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 113 The execution time of this command is shown below. DBCA-206480 about 15 min DBCA-204860 about 12 min DBCA-203240 about 8 min Command Descriptions...

  • Page 114: Identify Device (Ech)

    12.6 Identify Device (ECh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 115 W o r d C o n t e n t D e s c r i p t i o n 0 4 5 A H D r i v e c l a s s i f i c a t i o n , b i t a s s i g n m e n t s : 1 5 ( = 0 ) : 1 = A T A P I d e v i c e , 0 = A T A d e v i c e 1 4 ( = 0 ) : 1 = f o r m a t s p e e d t o l e r a n c e g a p r e q u i r e d 1 3 ( = 0 ) : 1 = t r a c k o f f s e t o p t i o n a v a i l a b l e...
  • Page 116 W o r d C o n t e n t D e s c r i p t i o n 4 0 0 0 H C a p a b i l i t i e s 1 5 ( = 0 ) 0 = t h e c o n t e n t s o f w o r d 5 0 a r e v a l i d 1 4 ( = 1 ) 1 = t h e c o n t e n t s o f w o r d 5 0 a r e v a l i d 1 ( = 0 ) R e s e r v e d 0 ( = 0 ) 1 = t h e d e v i c e h a s a m i n i m u m S t a n d b y t i m e r...
  • Page 117 W o r d C o n t e n t D e s c r i p t i o n 6 9 7 9 0 0 0 0 H R e s e r v e d 0 0 1 E H M a j o r v e r s i o n n u m b e r 0 ( = 1 E ) A T A 1 , A T A 2 , A T A 3 a n d A T A / A T A P I 4 0 0 1 7 H...
  • Page 118 W o r d C o n t e n t D e s c r i p t i o n 7 4 X X H C o m m a n d s e t / f e a t u r e e n a b l e d 1 5 ( = 0 ) R e s e r v e d 1 4 ( = 1 ) 1 = N O P c o m m a n d s u p p o r t e d 1 3 ( = 1 ) 1 = R E A D B U F F E R c o m m a n d s u p p o r t e d...
  • Page 119 W o r d C o n t e n t D e s c r i p t i o n X X X X H C u r r e n t M a s t e r P a s s w o r d R e v i s i o n C o d e s 9 3 1 2 7 0 0 0 0 H R e s e r v e d...
  • Page 120 M i c r o c o d e r e v i s i o n B C x O A x x x D B C A 2 0 6 4 8 0 N u m b e r o f c y l i n d e r s 3 4 7 0 h N u m b e r o f h e a d s 0 0 0 F h...

  • Page 121: Identify Device Dma (Eeh)

    12.7 Identify Device DMA (EEh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 122: Idle (E3H/97H)

    12.8 Idle (E3h/97h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 123: Idle Immediate (E1H/95H)

    12.9 Idle Immediate (E1h/95h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 124: Initialize Device Parameters (91H)

    12.10 Initialize Device Parameters (91h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 125: Read Buffer (E4H)

    12.11 Read Buffer (E4h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 126: Read Dma (C8H/C9H)

    12.12 Read DMA (C8h/C9h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 127 The head number of the first sector to be transferred. ( L = 0 ) In LBA mode, this register specifies LBA bits 24-27 to be transferred. ( L = 1 ) The retry bit. If set to one, then retries are disabled. Input Parameters From The Device Sector Count The number of requested sectors not transferred.

  • Page 128: Read Long (22H/23H)

    12.13 Read Long (22h/23h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 129 The head number of the sector to be transferred. ( L = 0 ) In LBA mode, this register contains LBA bits 24-27. ( L = 1 ) The retry bit. If set to one, then retries are disabled. Input Parameters From The Device Sector Count The number of requested sectors not transferred.

  • Page 130: Read Multiple (C4H)

    12.14 Read Multiple (C4h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 131 Input Parameters From The Device Sector Count The number of requested sectors not transferred. This will be zero, unless an unre- coverable error occurs. Sector Number The sector number of the last transferred sector. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 132: Read Native Max Address (F8H)

    12.15 Read Native Max Address (F8h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 133 Valid. Indicates that the bit is part of an input parameter and will be set to 0 or 1 by the device. Indicates that the bit is not used. Command Descriptions...

  • Page 134: Read Sectors (20H/21H)

    12.16 Read Sectors (20h/21h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 135 Input Parameters From The Device Sector Count The number of requested sectors not transferred. This will be zero, unless an unre- coverable error occurs. Sector Number The sector number of the last transferred sector. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 136: Read Verify Sectors (40H/41H)

    12.17 Read Verify Sectors (40h/41h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 137 Input Parameters From The Device Sector Count The number of requested sectors not verified. This will be zero, unless an unrecover- able error occurs. Sector Number The sector number of the last transferred sector. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 138: Recalibrate (1Xh)

    12.18 Recalibrate (1xh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 139: Security Disable Password (F6H)

    12.19 Security Disable Password (F6h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 140: Security Erase Prepare (F3H)

    12.20 Security Erase Prepare (F3h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 141: Security Erase Unit (F4H)

    12.21 Security Erase Unit (F4h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 142 Identifier Zero indicates that the device should check the supplied password against the user password stored internally. One indicates that the device should check the given pass- word against the master password stored internally. The Security Erase Unit command erases all user data and disables the security mode feature (device lock function).

  • Page 143: Security Freeze Lock (F5H)

    12.22 Security Freeze Lock (F5h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 144: Security Set Password (F1H)

    12.23 Security Set Password (F1h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 145 W o r d D e s c r i p t i o n C o n t r o l w o r d b i t 0 : I d e n t i f i e r ( 1 M a s t e r , 0 U s e r ) b i t 1 7...

  • Page 146: Security Unlock (F2H)

    12.24 Security Unlock (F2h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 147 W o r d D e s c r i p t i o n C o n t r o l w o r d b i t 0 : I d e n t i f i e r ( 1 M a s t e r , 0 U s e r ) b i t 1 1 5...

  • Page 148: Seek (7Xh)

    12.25 Seek (7xh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 149: Set Features (Efh)

    12.26 Set Features (EFh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 150 AAH Enable read look-ahead feature BBH 4 bytes of ECC apply on Read Long/Write Long commands CCH Enable reverting to power on defaults Warning 1. Hard reset or power off must not be done in 5 seconds after write command completion when write cache is enabled. Note 1.

  • Page 151: Set Max Address (F9H)

    12.27 Set Max Address (F9h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 152 Sector Number In LBA mode, this register contains LBA bits 0 - 7 which is to be input.(L=1) In CHS mode, this register is ignored. ( L = 0 ) Cylinder High/Low In LBA mode, this register contains LBA bits 8 - 15 (Low), 16 - 23 (High) which is to be set.

  • Page 153: Set Multiple (C6H)

    12.28 Set Multiple (C6h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 154: Sleep (E6H/99H)

    12.29 Sleep (E6h/99h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 155: Function Set (B0H)

    12.30 S.M.A.R.T. Function Set (B0h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 156 SMART Return Status 12.30.1.1 SMART Read Attribute Values (Subcommand D0h) This subcommand returns the device's Attribute Values to the host. Upon receipt of the SMART Read Attribute Values subcommand from the host, the device asserts BSY, saves any updated Attribute Values to the Attribute Data sectors, asserts DRQ, clears BSY, asserts INTRQ, and then waits for the host to transfer the 512 bytes of Attribute Value information from the device via the Data Register.
  • Page 157 12.30.1.5 SMART Execute Off-line Immediate (Subcommand D4h) This subcommand causes the device to immediately initiate the set of off-line data collection activities that collect attribute data in an off-line mode. Upon receipt of the subcommand from the host, the device sets BSY to one, begins its set of off-line data collection activities, clears BSY to zero and asserts INTRQ.

  • Page 158: Device Attributes Data Structure

    and will be aborted by the device (including the SMART Disable Operations subcommand), returning the error code as specified in Figure 105 on page 159. Any Attribute Values accumulated and saved to volatile memory prior to receipt of the SMART Disable Operations command will be preserved in the device's Attribute Data Sectors.

  • Page 159: Individual Attribute Data Structure

    D e s c r i p t i o n B y t e s O f f s e t F o r m a t V a l u e D a t a S t r u c t u r e R e v i s i o n N u m b e r 0 0 h b i n a r y 0 0 0 5 h...
  • Page 160 D e s c r i p t i o n B y t e s O f f s e t F o r m a t A t t r i b u t e I D N u m b e r ( 0 1 h t o F F h ) 0 0 h b i n a r y S t a t u s F l a g s...
  • Page 161 Seek Error Rate Seek Time Performance (*) Power-On Hours Count Spin Retry Count Device Power Cycle Count C R C Error Count Disk Shift G-Sense Error Rate Loaded Hours Load Retry Count Load Friction Load Cycle Count Load-in Time Torq-amp Count Power-off Retract Count Command Descriptions...
  • Page 162 12.30.2.2.2 Status Flag Definitions B i t F l a g N a m e D e f i n i t i o n P r e F a i l u r e / I f b i t = 0 , a n A t t r i b u t e V a l u e l e s s t h a n o r A d v i s o r y b i t e q u a l t o i t s c o r r e s p o n d i n g A t t r i b u t e T h r e s h o l d i n d i c a t e s a n A d v i s o r y c o n d i t i o n...
  • Page 163 Segment completed without error All segments completed without errors. In this case, current segment pointer equals to total seg- ments required. Off-line data collecting aborted by interrupting command Off-line data collection aborted with fatal error 12.30.2.4 Total Segments Required for Off-line Data Collection The device will return 01h as the total segments for off-line data collection.

  • Page 164: Device Attribute Thresholds Data Structure

    12.30.2.8 S.M.A.R.T. Capability This word of bit flags describes the S.M.A.R.T. capabilities of the device. The device will return 03h as its S.M.A.R.T. capability which means: Definition Power mode attribute saving capability If bit = 1, the device will save its Attribute Values prior to going into a power saving mode (Standby or Sleep mode).
  • Page 165 D e s c r i p t i o n B y t e s O f f s e t F o r m a t V a l u e D a t a S t r u c t u r e R e v i s i o n N u m b e r 0 0 h b i n a r y 0 0 0 5 h...

  • Page 166: Error Reporting

    D e s c r i p t i o n B y t e s O f f s e t F o r m a t A t t r i b u t e I D N u m b e r ( 0 1 h t o F F h ) 0 0 h b i n a r y A t t r i b u t e T h r e s h o l d ( f o r c o m p a r i s o n w i t h...
  • Page 167 E r r o r C o n d i t i o n S t a t u s E r r o r R e g i s t e r R e g i s t e r A S .

  • Page 168: Standby (E2H/96H)

    12.31 Standby (E2h/96h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 169: Standby Immediate (E0H/94H)

    12.32 Standby Immediate (E0h/94h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 170: Write Buffer (E8H)

    12.33 Write Buffer (E8h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 171: Write Dma (Cah/Cbh)

    12.34 Write DMA (CAh/CBh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 172 The head number of the first sector to be transferred. ( L = 0 ) In LBA mode, this register contains LBA bits 24 - 27. ( L = 1 ) The retry bit. If set to one, then retries are disabled. When write cache is enabled, They are ignored.

  • Page 173: Write Long (32H/33H)

    12.35 Write Long (32h/33h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 174 Input Parameters From The Device Sector Count The number of requested sectors not transferred. Sector Number The sector number of the sector to be transferred. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the sector to be transferred.

  • Page 175: Write Multiple (C5H)

    12.36 Write Multiple (C5h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 176 Input Parameters From The Device Sector Count The number of requested sectors not transferred. This will be zero, unless an unre- coverable error occurs. Sector Number The sector number of the last transferred sector. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 177: Write Sectors (30H/31H)

    12.37 Write Sectors (30h/31h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 178 Input Parameters From The Device Sector Count The number of requested sectors not transferred. This will be zero, unless an unre- coverable error occurs. Sector Number The sector number of the last transferred sector. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 179: Write Verify (3Ch: Vendor Specific)

    12.38 Write Verify (3Ch: Vendor Specific) In DBCA-2xxxxx implementation, Write Verify command is exactry same as Write Sectors command(30h). No read verification is performed after write operation. Refer to Write Sectors Command for parameters. Command Descriptions...
  • Page 180 O E M Specifications of DBCA-2xxxxx 2.5 inch H D D...

  • Page 181: Timeout Values

    3 0 s e c C o m m a n d C o m p l e t e B S Y = 1 ( N o t e . 2 ) Figure 113. Timeout Values -- continued -- Copyright IBM Corp. 1998...
  • Page 182 F U N C T I O N I N T E R V A L S T A R T S T O P T I M E O U T D M A D a t a D e v i c e B u s y a f t e r O u t t o C o m m a n d S t a t u s R e g i s t e r 4 0 0 n s...

  • Page 183: Appendix

    N o t t o b e u s e d A 2 h S E R V I C E N o t t o b e u s e d Figure 115. Command coverage -- continued -- Copyright IBM Corp. 1998...
  • Page 184 C o m m a n d C o m m a n d I m p l e m e n t a t i o n A T A 4 C a t e g o l y C o d e N a m e f o r D B C A 2 x x x x x...

  • Page 185: Set Features Command Support Coverage

    14.2 SET FEATURES Command Support Coverage The following table is provided to facilitate the understanding of DBCA-2xxxxx "Set Features" command support coverage comparing to the ATA-4 defined command set. The column of 'Implementation' shows the capability of DBCA-2xxxxx for those commands. For detail operation, refer to 12.26, “Set Features (EFh)”...
  • Page 186 O E M Specifications of DBCA-2xxxxx 2.5 inch H D D...

  • Page 187: Index

    92, 104 Read Verify Sectors (40h/41h) Recalibrate (1xh) S.M.A.R.T. Function Set (B0h) Security Disable Password (F6h) Security Erase Prepare (F3h) Security Erase Unit (F4h) Security Freeze Lock (F5h) Security Set Password (F1h) Security Unlock (F2h) Seek (7xh) Copyright IBM Corp. 1998...
  • Page 188 Register (continued) Device/Head Register Drive Address Register Error Register Features Register Register Initialization ICRCE Sector Count Register Identify Device 89, 106 Sector Number Register Identify Device D M A 93, 113 Status Register Idle 92, 114 Register Initialization Idle Immediate 92, 115 Reset I D N...
  • Page 189 Timeout Interval Timeout Parameter 114, 160 Timeout Values TK0NF Write Buffer 90, 162 Write Cache Write D M A 93, 163 Write Long 90, 165 Write Multiple 90, 167 Write Sectors 90, 169 Write Verify 91, 171 W T G Index...
  • Page 190 S25L-2426-02 Published in Japan...

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