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7.3 Signal definitions
The pin assignments of interface signals are listed as follows:Signal definitions
Table 24: Signal definitions
PIN
SIGNAL
01
RESET-
03
DD07
05
DD06
07
DD05
09
DD04
11
DD03
13
DD02
15
DD01
17
DD00
19
GND
21
DMARQ
23
DIOW-(*)
25
DIOR-(*)
27
IORDY(*)
29
DMACK-
31
INTRQ
33
DA01
35
DA00
37
CS0-
39
DASP-
41
+ 5V logic
43
GND
O
I
I/O
OD
power
reserved
The signal lines marked with (*) are redefined during the Ultra DMA protocol to provide special functions. These
lines change from the conventional to special definitions at the moment the host decides to allow a DMA burst, if
the Ultra DMA transfer mode was previously chosen via SetFeatures. The drive becomes aware of this change
upon assertion of the DMACK- line. These lines revert back to their original definitions upon the deassertion of
DMACK at the termination of the DMA burst.
I/O
Type
I
TTL
I/O
3–state
I/O
3–state
I/O
3–state
I/O
3–state
I/O
3–state
I/O
3–state
I/O
3–state
I/O
3–state
O
3–state
I
TTL
I
TTL
O
3–state
I
TTL
O
3–state
I
TTL
I
TTL
I
TTL
I/O
OD
power
designates an output from the drive
designates an input to the drive
designates an input/output common
designates an Open-Drain output
designates a power supply to the drive
designates reserved pins which must be left unconnected
Travelstar 7K100 Hard Disk Drive Specification
PIN
SIGNAL
02
GND
04
DD08
06
DD09
08
DD10
10
DD11
12
DD12
14
DD13
16
DD14
18
DD15
(20)
Key
22
GND
24
GND
26
GND
28
CSEL
30
GND
32
Reserved
34
PDIAG-
36
DA02
38
CS1-
40
GND
42
+ 5V motor
44
(reserved)
36
I/O
Type
I/O
3–state
I/O
3–state
I/O
3–state
I/O
3–state
I/O
3–state
I/O
3–state
I/O
3–state
I/O
3–state
I
TTL
I/O
OD
I
TTL
I
TTL
power
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