Chipset; Overview; Amd I/O Bridges; Hypertransport 3 (Ht-3) - Dell PowerEdge M915 Technical Manual

Dell
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Chipset

8.1 Overview

The Dell™ PowerEdge™ M915 chipset has a dual I/O Bridge (IOB) configuration with AMD SR5670 IO
bridges and the SP5100 Southbridge. The SR5670 is designed to support AMD's G34 processor family,
HyperTransport 3 Interface (2.6 GHz), DDR3 memory technology, and PCI Express Generation 2.

8.2 AMD I/O Bridges

The PowerEdge M915 I/O Board uses two AMD SR5670 IOBs to provide links between the G34
processor(s) and I/O components. The main components of the I/O controllers are configured to use
two x16 HyperTransport 3 link (to CPU1 and CPU2), up to 52 lanes of PCI Express Gen 2, a x4 PCIe
Gen 1 Southbridge Interface (SB Link) and an integrated IOAPIC. CPU1 has direct HT3 link to IOB1 and
CPU2 has direct HT3 link to IOB2. IOB1 has the Southbridge interface.

8.3 HyperTransport 3 (HT-3)

The HyperTransport 3 (HT-3) consists of serial point-to-point interconnects for the processors and the
I/O bridges. PowerEdge M915 has a total of four HT-3 links per processor, which allows
interconnecting each processor and an option for I/O bridge. Each I/O bridge has a single x16 HT-3
link. A full Link consists of 16 lanes (full-width) in each direction with a link speed of 6.4 GT/s. The
HT-3 clocking for CPU HT-3 and IOB HT-3 are 3.2GHz and 2.6GHz, respectively. Therefore, the IOB
HT-3 link is capable of 5.2 GT/s. For routing, the HT-3 links are grouped by x8 Command Address
(CAD), x1 Control (CTL), and x1 Clock (CLK) for each RX and TX directions.
8.4 SouthBridge
The SB Link connects the SR5670 IOB with the AMD Southbridge SP5100. The SB Link (A-Link Express)
is equivalent to an x4 PCI-e Gen 1 link with a transfer rate of 1 GB/s in each direction.

8.5 AMD SP5100 SouthBridge

The AMD SP5100 is a highly integrated Southbridge controller, supporting the following functions:

PCI Bus 32-bit Interface Rev 2.3 running at 33 MT/s

Serial ATA (SATA) ports with transfer rates up to 300 MB/s

Five OHC (full-speed 1.1) and two EHCI (high-speed 2.0) USB host controllers, with up to 12
USB general purpose ports and 2 USB embedded ports. (The PowerEdge M915 uses eight of
these ports for internal and external use from the general purpose ports.)

Power management interface (ACPI 3.0b compliant)

Integrated Micro Controller (IMC) and thermal management. (The iDRAC interfaces the
Hardware Thermal Control [HTC] on PowerEdge M915, not the SP5100.)

I/O interrupt controller

SMBus 2.0 controller

Low Pin Count (LPC) interface to Super I/O, Trusted Platform Module (TPM), and SPI-VU

Serial Peripheral Interface (SPI) support for up to two devices (A 4 MB BIOS flash is connected
to the SP5100 using SPI interface.)
PowerEdge M915 Technical Guide
Link Interface
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