Table of Contents
Advertisement
Table 5.16 Ultra DMA data burst timing requirements (2 of 2)
NAME
MODE 0
(in ns)
MIN
MAX
MIN
t
0
0
ZIORDY
t
20
20
ACK
t
50
50
SS
Notes:
1) Unless otherwise specified, timing parameters shall be measured at the connector of the sender or receiver to which the parameter applies
(see Note 5 for exceptions). For example, the sender shall stop generating STROBE edges t
STROBE and DMARDY- timing measurements are taken at the connector of the sender.
2) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.
3) t
, t
and t
indicate sender-to-recipient or recipient-to-sender interlocks, i.e., one agent (either sender or recipient) is waiting for the
UI
MLI
LI
other agent to respond with a signal before proceeding. t
time-out that has a defined minimum. t
4) Special cabling shall be required in order to meet data setup (t
5) Timing for t
and t
shall be met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value.
DVS
DVH
MODE 1
MODE 2
(in ns)
(in ns)
MAX
MIN
MAX
0
20
50
is an unlimited interlock that has no maximum time value. t
UI
is a limited time-out that has a defined maximum.
LI
DS
C141-E106-01EN
MODE 3
MODE 4
(in ns)
(in ns)
MIN
MAX
MIN
MAX (see Notes 1 and 2)
0
0
20
20
50
50
after the negation of DMARDY-. Both
RFS
) and data hold (t
) times in modes 3 and 4.
DH
COMMENT
Minimum time before driving
IORDY
Setup and hold times for DMACK-
(before assertion or negation)
Time from STROBE edge to negation
of DMARQ or assertion of STOP
(when sender terminates a burst)
is a limited
MLI
5 - 89
Advertisement
Table of Contents
