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At command issuance (I/O registers setting contents)
1F7
(CM)
H
1F6
(DH)
H
1F5
(CH)
H
1F4
(CL)
H
1F3
(SN)
H
1F2
(SC)
H
1F1
(FR)
H
At command completion (I/O registers contents to be read)
1F7
(ST)
H
1F6
(DH)
H
1F5
(CH)
H
1F4
(CL)
H
1F3
(SN)
H
1F2
(SC)
H
1F1
(ER)
H
(26)
SLEEP (X'99' or X'E6')
This command is the only way to make the device enter the sleep mode.
Upon receipt of this command, the device sets the BSY bit of the Status register and enters the
sleep mode. The device then clears the BSY bit and generates an interrupt. The device generates
an interrupt even if the device has not fully entered the sleep mode.
In the sleep mode, the spindle motor is stopped and the ATA interface section is inactive. All
I/O register outputs are in high-impedance state.
The only way to release the device from sleep mode is to execute a software or hardware reset.
At command issuance (I/O registers setting contents)
1F7
(CM)
H
1F6
(DH)
H
1F5
(CH)
H
1F4
(CL)
H
1F3
(SN)
H
1F2
(SC)
H
1F1
(FR)
H
5 - 46
X'94' or X'E0'
DV
xx
xx
xx
xx
xx
xx
Status information
DV
xx
xx
xx
xx
xx
Error information
X'99' or X'E6'
DV
xx
xx
xx
xx
xx
xx
C141-E106-01EN
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