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AAN95.
No_Soft_Reset Bit in the PMCSR Does Not Operate as Expected
Problem:
When the No_Soft_Reset bit in the Power Management Control and Status Register
(PMCSR; Bus 0; Devices 0, 3, 4, 5; Function 0; Offset 0xE4; Bit 3) is cleared the device
should perform an internal reset upon transitioning from D3
erratum the device does not perform an internal reset upon transitioning from D3
D0.
Implication:
When the No_Soft_reset bit in the PMCSR register is set or cleared no internal reset of
the device will be preformed when transitioning from D3
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN96.
VM Exits Due to LIDT/LGDT/SIDT/SGDT Do Not Report Correct
Operand Size
Problem:
When a VM exit occurs due to a LIDT, LGDT, SIDT, or SGDT instruction with a 32-bit
operand, bit 11 of the VM-exit instruction information field should be set to 1. Due to
this erratum, this bit is instead cleared to 0 (indicating a 16-bit operand).
Implication:
Virtual-machine monitors cannot rely on bit 11 of the VM-exit instruction information
field to determine the operand size of the instruction causing the VM exit.
Workaround:
Virtual-machine monitor software may decode the instruction to determine operand
size.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN97.
PCIConfigRd() and PCIConfigWr() PECI Commands May Silently Fail
During Package C6 Exit Events
Problem:
When PCIConfigRd() or PCIConfigWr() commands coincide with processor package C6
exits under the right timing conditions, they may fail to execute but still produce
'passing' responses.
Implication:
When the timing conditions of this erratum are met, reads will return a value of "all
zeroes" for the return data and writes will have no effect while both commands will
return a passing completion code. The rate of occurrence of this issue is dependent on
frequency and duration of C6 entry/exit events and PECI polling rate.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN98.
Performance Monitoring Events STORE_BLOCKS.NOT_STA and
STORE_BLOCKS.STA May Not Count Events Correctly
Problem:
Performance Monitor Events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA
should only increment the count when a load is blocked by a store.
erratum, the count will be incremented whenever a load hits a store, whether it is
blocked or can forward. In addition this event does not count for specific threads
correctly.
Implication:
If Intel® Hyper-Threading Technology is disabled, the Performance Monitor events
STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA may indicate a higher occurrence
of loads blocked by stores than have actually occurred. If Intel Hyper-Threading
Technology is enabled, the counts of loads blocked by stores may be unpredictable and
they could be higher or lower than the correct count.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
to D0. Due to this
hot
to D0.
hot
Due to this
to
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45
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