Table 5.2 I/O Registers - Fujitsu MHR2010AT Product Manual

5.2.1 I/O registers
Communication between the host system and the device is done through input-
output (I/O) registers of the device.
These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to
DA2 from the host system. Table 5.2. shows the coding address and the function
of I/O registers.
CS0– CS1– DA2
Command block registers
L H L
L H L
L H L
L H L
L H H
L H H
L H H
L H H
L L X
Control block registers
H L H
H L H
Notes:
1. The Data register for read or write operation can be accessed by 16 bit data
bus (DATA0 to DATA15).
2. The registers for read or write operation other than the Data registers can be
accessed by 8 bit data bus (DATA0 to DATA7).
3. When reading the Drive Address register, bit 7 is high-impedance state.
4. H indicates signal level High and L indicates signal level Low.
There are two methods for specifying the LBA mode. One method is to
specify the LBA mode with 28-bit address information, and the other is to
specify it with 48-bit address information (command of EXT system). If
the LBA mode is specified with 28-bit address information, the
C141-E145-02EN

Table 5.2 I/O registers

DA1 DA0
Read operation
L L Data
L H Error Register
H L Sector Count
H H Sector Number
L L Cylinder Low
L H Cylinder High
H L Device/Head
H H Status
X X (Invalid)
H L Alternate Status
H H —
5.2 Logical Interface
I/O registers
Write operation
Data
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
(Invalid)
Device Control
—
Host I/O
address
X'1F0'
X'1F1'
X'1F2'
X'1F3'
X'1F4'
X'1F5'
X'1F6'
X'1F7'
—
X'3F6'
X'3F7'
5-7