Contents
5.5.3
5.5.4
5.5.5
5.5.6
5.6
5.6.1
5.6.2
5.6.3
5.6.3.2 Ultra DMA data burst timing requirements
5.6.4
CHAPTER 6
Operations ................................................................................. 6-1
6.1
6.1.1
6.1.2
6.1.3
xii
5-127
PIO data transfer
5-127
5-142
Response to power-on
Response to hardware reset
Response to software reset
5-116
5-116
5-117
5-117
5-118
5-121
5-121
5-121
5-122
5-123
5-125
5-126
5-128
5-129
5-129
5-130
5-133
5-134
5-137
5-138
6-2
6-2
6-3
6-5
5-135
5-136
5-139
5-140
5-141
C141-E145-02EN