Sharp R-21JV-F Service Manual page 23

Pin No. Signal
61 P33 OUT
62 P32 OUT
63 P31 OUT
64 P30 OUT
X24C02 is a 2K-bit, serial memory, enabling CMOS to be erased/written electrically. This memory is constructed with 256 registers
x 8bits, enabling individual access, read and write operations to be performed. Details of input/output signal for IC2 are as shown
in the following diagram.
TOP VIEW
A0 1
A1 2
A2 3
VSS
4
Pin No. Signal
1-3 A0-A2
4 VSS
5 SDA
6 SCL
7 TEST
8 VCC
I/O
Key strobe signal.
Signal applied to touch-key section. A pulse signal is input to P27, P26, P25 and P24
terminals while one of G5 line keys on key matrix is touched.
Key strobe signal.
Signal applied to touch-key section. A pulse signal is input to P27, P26, P25 and P24
terminals while one of G6 line keys on key matrix is touched.
Key strobe signal.
Signal applied to touch-key section. A pulse signal is input to P27, P26, P25 and P24
terminals while one of G7 line keys on key matrix is touched.
Key strobe signal.
Signal applied to touch-key section. A pulse signal is input to P27, P26, P25 and P24
terminals while one of G8 line keys on key matrix is touched.
2-2 Memory IC (IC2)
VCC
8
TEST
7
SCL
6
SDA
5
Figure T-4 Relation between Pin Numbers, and Signals
I/O
IN Connected to +5V.
IN Connected to GND.
IN/OUT Serial data input/output : input/outputs data to IC1.
IN Clock signal input : input/outputs sireal data at every one pulse.
IN Connected to GND.
IN Connected to +5V.
Description
FUNCTIONAL DIAGRAM
(3) Vcc
(4) Vss
(5) SDA
START
STOP
LOGIC
SLAVE ADDRESS
REGISTER
(6) SCL
COMPARATOR
LOAD
ADDRESS
COUNTER
R/W
Dout
ACK
Description
21
H.V. GENERATION
START CYCLE
TIMING
& CONTROL
CONTROL
LOGIC
2
E PROM
64
256 x 8
XDEC
INC
WORD
1
64
5
3
YDEC
8
CK
PIN
DATA REGISTER
R-21HT-F
R-21JV-F
Dout