Invlpg Instruction Does Not Flush Entire Four-Megabyte Page Properly With Certain Linear Addresses - AMD Athlon 6 Revision

24332E—December 2002
16 INVLPG Instruction Does Not Flush Entire Four-Megabyte Page Properly with Certain
Linear Addresses
Products Affected. A0, A2
Normal Specified Operation. After executing an INVLPG instruction the TLB should not contain any
translations for any part of the page frame associated with the designated logical address.
Non-conformance. When the logical address designated by the INVLPG instruction is mapped by a 4-
Mbyte page mapping and LA[21] is equal to one it is possible that the TLB will still retain translations
after the instruction has finished executing.
Potential Effect on System. The residual data in the TLB can result in unexpected data access to stale or
invalid pages of memory.
Suggested Workaround. When using the INVLPG instruction in association with a page that is mapped via
a 4-Mbyte page translation, always clear bit 21.
Resolution Status. Fix planned for a future revision.
Preliminary Information
AMD Athlon™ Processor Model 6 Revision Guide
7