Pbsram (Pipelined Burst Sram); Dimm; Pc-1600 / Pc-2100/ Pc-2700 / Pc-3200 Ddr Dram - AOpen MX4GVR Online Manual

M X 4 G V R
M X 4 G V R
P B S R A M ( P i p e l i n e
P B S R A M ( P i p e l i n e
For Socket 7 CPU, one burst data read requires four QWord (Quad-word, 4x16 = 64 bits). PBSRAM only needs one address
decoding time and automatically sends the remaining QWords to CPU according to a predefined sequence. Normally, it is 3-1-1-1,
total 6 clocks, which is faster than asynchronous SRAM. PBSRAM is often used on L2 (level 2) cache of Socket 7 CPU. Slot 1 and
Socket 370 CPU do not need PBSRAM.
P C - 1 0 0 D I M M
P C - 1 0 0 D I M M
SDRAM DIMM that supports 100MHz CPU
P C - 1 3 3 D I M M
P C - 1 3 3 D I M M
SDRAM DIMM that supports 133MHz CPU
P C - 1 6 0 0 / P C - 2 1 0 0
P C - 1 6 0 0 / P C - 2 1 0 0
Based on FSB frequency, the DDR DRAM has 200MHz, 266MHz and 333 MHz three types of working frequency. Because of DDR
DRAM data bus is 64-bit, it provides data transfer bandwidth up to 200x64/8=1600MB/s, 266x64/8=2100MB/s, 333x64/8=2700MB/s
and 400x64/8=3200MB/s. Hence, the PC-1600 DDR DRAM is working with 100MHz, PC-2100 DDR DRAM is working with 133MHz,
PC-2700 DDR DRAM is working with 166MHz and PC-3200 DDR DRAM is working with 200MHz FSB frequency.
d B u r s t S R A M )
d B u r s t S R A M )
FSB bus clock.
FSB bus clock.
/ P C - 2 7 0 0 / P C - 3 2 0
/ P C - 2 7 0 0 / P C - 3 2 0
0 D D R D R A M
0 D D R D R A M
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O n l i n e M a n u a l
O n l i n e M a n u a l