Register Description - Philips TEA5880TS Manual

Philips Semiconductors

8.1 Register description

9397 750 13022
Preliminary data sheet
Table 5: TEA5880TS registers description
Address Register name
0000b VADC
0001b CTRL_C
0010b CTRL_A
0011b OSC_STEREO
0100b CTRL_B
0101b CAP_FM
0110b OSC_IF
0111b OSC_FM
- STATUS
- COUNTER
Table 6: VADC - (address 0h) bit description
Bit Symbol
14 to 11 -
10 to 6 VADC2[4:0]
5 -
4 to 0 VADC1[4:0]
Table 7: CTRL_C - (address 1h) bit description
Bit Symbol
14 to 11 -
10 and 9 -
8 -
7 to 4 -
3 to 1 -
0 -
[1] The application should write logic 0 to this register at start-up to ensure that the device functions correctly.
Table 8: Time delay selection
Value
000b
001b
010b
011b
100b
101b
110b
111b
Integrated FM stereo radio IC for host processor tuning
Access
write only
write only
write only
write only
write only
write only
write only
write only
read only
read only
Description
address bits
controls the width filter
not applicable; should be written to logic 0
controls the center filter
Description
address bits
reserved for production test; should be written to logic 0
reserved for swapping counters1 and 2; should be written to logic 0
not applicable; should be written to logic 0
reserved for time delay selection (counter 2); application should keep
bits 3 to 1 at logic 0; see
reserved for enable counter 2; should be written to logic 0
Decimal
0
1
2
3
4
5
6
7
Rev. 02 — 26 April 2004
TEA5880TS
Operation Data width
VADC register 11 bits
control register C 11 bits
control register A 11 bits
oscillator stereo 11 bits
decoder clock
control register B 11 bits
capacitor bank FM 11 bits
oscillator IF 11 bits
oscillator FM 11 bits
status register 16 bits
counter register 16 bits
[1]
Table 8
Stop value
count 2
count 8
count 32
count 128
count 512
count 2048
count 8192
count 32768
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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