Stereo Decoder; Digital Interface (3-Wire Bus) - Philips TEA5880TS Manual

Philips Semiconductors

7.8 Stereo decoder

8. Digital interface (3-wire bus)

9397 750 13022
Preliminary data sheet
The PLL stereo decoder is adjustment free. The stereo decoder can be switched to mono
via the digital interface.
The TEA5880TS has a 3-wire bus with read/write, clock and data line.
The register set of the TEA5880TS can be accessed via the digital interface.
The pins given in Table 4
Table 4: Digital interface pins
Pin number Name
Pin 6 R/W
Pin 8 CLOCK
Pin 7 DATA
DATA
R/W
enable
counter 1
Fig 4. Digital interface block diagram.
Integrated FM stereo radio IC for host processor tuning
are defined for the digital interface of the TEA5880TS.
Type Description
input LOW is read from TEA5880TS;
HIGH is write to TEA5880TS
input clock
input/output bidirectional data
R/W
stereo LED
OUTPUT stereo clock
SOURCE IF OSC
SELECTOR FM OSC
CLOCK
15 BITS SIPO (SERIAL IN PARALLEL OUT)
4 bits data
ADDRESS
DECODER
COUNTER 1 (16 bits)
16 bits data
16 BITS PISO (PARALLEL IN SERIAL OUT)
CLOCK
Rev. 02 — 26 April 2004
TEA5880TS
R/W
11 bits data
CONTROL
control bits
REGISTER A
CONTROL control bits
REGISTER B
CONTROL
control bits
REGISTER C
REST OF THE
control bits
REGISTERS
STATUS REGISTER
16 bits data
1-bit data
R/W
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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