Block Diagram - Fujitsu MB39A104 Datasheet

MB39A104

■ BLOCK DIAGRAM

−INE1
10
10 µA
CS1 11
FB1 9
DTC1 6
−INE2
15
10 µA
CS2 14
FB2 16
DTC2 19
CSCP 8
4
VREF
Error
Amp1
+
+
1.24 V
L priority
VREF
Error
Amp2
+
+
1.24 V
L priority
H priority
H: at SCP
SCP
Comp.
+
+
(3.1 V)
SCP
Logic
UVLO
H:UVLO
release
OSC
12 13
RT CT
CH1
L priority
PWM
Comp.1
+
Drive1
+
P-ch
= 200 mA
I
O
at VCCO = 12 V
Current
Protection
Logic
CH2
L priority
PWM
Comp.2
+
Drive2
+
P-ch
= 200 mA
I
O
at VCCO = 12 V
Current
Protection
Logic
H: at OCP
VH
Bias
Voltage
2.5 V
Error Amp Power Supply
1.5 V
Error Amp Referennce
1.24 V
bias
ON/OFF
VREF VR1
Accuracy
±1%
5.0 V
17 18
VREF GND
1 VCCO
3 OUT1
4 VS1
+
5 ILIM1
22 OUT2
21 VS2
+
20 ILIM2
− 5 V
V
CC
2 VH
23 GNDO
7 VCC
Power
24 CTL
CTL