Cisco CX-FEIP-1FX= Installation and con?guration Installation Manual page 6

Fast ethernet interface processor
Table of Contents

Advertisement

Installation Prerequisites
Guidelines for Interface Processor Installation and Removal
This section describes mechanical functions of system components, emphasizes the importance of
following correct procedures to avoid unnecessary board failures, and is for background only;
specific procedures follow in the section "FEIP Installation" on page 21.
You can remove and replace interface processors while the system is operating; you do not need to
notify the software or reset the system power. This functionality enables you to add, remove, or
replace interface processors with the system online, which provides a method that is seamless to end
users on the network, maintains all routing information, and ensures session preservation.
After an interface processor is reinstalled, the system brings on line only interfaces that match the
current configuration and were previously configured as up; all others require that you configure
them with the configure command.
Caution
insert only one interface processor at a time. Allow at least 15 seconds for the system to complete the
preceding tasks before removing or inserting another interface processor. Disrupting the sequence before the
system completes its verification can cause the system to interpret hardware failures.
Cisco 7000 series and Cisco 7500 series routers have ejector levers located on the ends of the
interface processor slots. (See Figure 1a.) The function of the ejector levers is to align and seat the
interface processor connectors in the backplane. Failure to use the ejector levers and insert the
interface processor properly can disrupt the order in which connector pins make contact with the
backplane.
Follow the FEIP installation and removal instructions carefully, and review the following examples
of incorrect insertion practices and their results:
Use the ejector levers when removing an interface processor to ensure that the backplane connector
pins disconnect from the interface processor in the sequence expected by the system. Any interface
processor that is only partially connected to the backplane can hang the bus. Steps for correctly
performing OIR are included with the following procedures for installing and removing the FEIP.
6 Fast Ethernet Interface Processor (FEIP) Installation and Configuration
The system can indicate a hardware failure if you do not follow proper procedures. Remove or
Using the handle to force the interface processor all the way into the slot can pop the ejector
levers out of their springs. If you then try to use the ejector levers to seat the interface processor,
the first layer of pins (which are already mated to the card or interface processor) can disconnect
and then remate with the backplane, which the system interprets as a board failure.
Using the handle to force or slam the interface processor all the way into the slot can damage the
pins on the board connectors if they are not aligned properly with the backplane.
When using the handle (rather than the ejector levers) to seat the interface processor in the
backplane, you might need to pull the interface processor back out and push it in again to align
it properly. Even if the backplane pins are not damaged, the pins mating with and disconnecting
from the card or interface processor might cause the system to interpret a board failure. Using the
ejector levers ensures that the board connector mates with the backplane in one continuous
movement.
Using the handle to insert or remove an interface processor, or failing to push the ejector levers
fully against the interface processor, can leave some (not all) of the connector pins mated to the
card or interface processor, a state which hangs the system. Using the ejector levers and making
sure that they are pushed fully into position ensures that all three layers of pins are mated with
(or free from) the backplane.

Advertisement

Table of Contents
loading

This manual is also suitable for:

Cx-feip-1txCx-feip-2fxCx-feip-2tx

Table of Contents