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Preliminary Information
TPDM
Serial I/O
Address
Channel
STi0, Ch0
000H
STi0, Ch1
001H
.
.
STi7, Ch30
0FEH
STi7, Ch31
0FFH
STo0 (STi8), Ch0
100H
STo0 (STi8), Ch1
101H
.
.
STo7 (STi15), Ch30
1FEH
STo7 (STi15), Ch31
1FFH
Figure 12a - 2.048 Mbps Add/Drop Mode TPDM
Addressing
Serial Output
RPCM
Channel
Address
STo0, Ch0
000H
STo0, Ch1
001H
.
.
STo7, Ch30
0FEH
STi7, Ch31
0FFH
STi0 (STo8), Ch0
100H
STi0 (STo8), Ch1
101H
.
.
STi7 (STo15), Ch30
1FEH
STi7 (STo15), Ch31
1FFH
Figure 12b - 2.048 Mbps Add/Drop Mode RPCM
Addressing
4.096 Mbps Mode
The 4.096 Mbps mode has 8 input and 8 output
streams, and 64 channels per stream. Therefore 3
bits are used to address the 8 streams, and 6 bits
are used to address the 64 channels. Figure 13a
shows how the Transmit Path Data Memory is read in
this mode. Each of the 512 input channels is mapped
to an address in the TPDM. CPU reads require the 2
LSBs of the CAR Register, and the 7 LSBs of the
address bus. The source-channel address-value
written in the TPCM requires 9 bits.
Figure 13b shows how the Receive Path Connection
Memory is addressed by the CPU in 4.096 Mbps
CPU Port Addressing:
CAR
Address Bus
1 0
6 5 4 3 2 1 0
Stream
Channel
TPCM Contents:
8 7 6 5
4 3 2 1 0
Stream
Channel
Bits 8:5 select one of 16 streams.
Bits 4:0 select one of 32 channels
per stream.
CPU Port Addressing:
CAR
Address Bus
6 5 4 3 2 1 0
1 0
Stream
Channel
mode. Each of the 512 output channels has a
control-address in the RPCM. CPU accesses require
the 2 LSBs of the CAR Register, and the 7 LSBs of
the address bus. Per-channel direction control in this
mode is the same as the 2.048 Mbps Balanced
mode.
TPDM
Serial Input
Address
Channel
STi0, Ch0
000H
STi0, Ch1
001H
.
.
STi7, Ch62
1FEH
1FFH
STi7, Ch63
Figure 13a - 4.096 Mbps TPDM Addressing
RPCM
Serial Output
Address
Channel
STo0, Ch0
000H
STo0, Ch1
001H
.
.
STo7, Ch62
1FEH
1FFH
STo7, Ch63
Figure 13b - 4.096 Mbps RPCM Addressing
8.192 Mbps Mode
The 8.192 Mbps mode has 4 input and 4 output
streams, and 128 channels per stream. Therefore 2
bits are used to address the 4 streams, and 7 bits
are used to address the 128 channels. Figure 14a
shows how the Transmit Path Data Memory is read in
this mode. Each of the 512 input channels is mapped
to an address in the TPDM. CPU reads require the 2
LSBs of the CAR Register, and the 7 LSBs of the
address bus. The source-channel address-value
written in the TPCM requires 9 bits.
Figure 14b shows how the Receive Path Connection
Memory is addressed by the CPU in 8.192 Mbps
mode. Each of the 512 output channels has a
control-address in the RPCM. CPU accesses require
the 2 LSBs of the CAR Register, and the 7 LSBs of
the address bus. Per-channel direction control in this
mode is the same as the 2.048 Mbps Balanced
mode.
MT90840
CPU Port Addressing:
CAR
Address Bus
1 0
6
5
4 3 2 1 0
Stream
Channel
TPCM Contents:
5
4 3 2 1 0
8 7 6
Channel
Stream
Bits 8:6 select one of 8 streams.
Bits 5:0 select one of 64 channels
per stream.
CPU Port Addressing:
CAR
Address Bus
1 0
6
5
4 3 2 1 0
Stream
Channel
2-249
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