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Features
•
Time slot interchange function between eight
pairs of ST-BUS/GCI/MVIP
channels) and parallel data port
•
Programmable data rates on the parallel port
(19.44, 16.384, or 6.480 Mbyte/s)
•
Programmable data rates on the serial port
(2.048 Mbps, 4.096 Mbps or 8.192 Mbps)
•
Supports star and point-to-point connections, and
unidirectional or bidirectional ring topologies for
distributed systems
•
Input-to-output bypass function on the parallel
data port for use in add/drop applications
•
Provides elastic buffer at parallel input port in the
receive direction
•
Provides byte switching for up to 2430 channels
•
Per-channel direction control on the serial port
side
•
Per-channel message mode and high-impedance
control on both parallel and serial port sides
•
8-bit multiplexed microprocessor port compatible
with Intel and Motorola microcontrollers
•
Guarantees frame integrity when switching nX64
wideband channels such as ISDN H0 channel
•
Provides external control lines allowing fast
parallel interface to be shared with other devices
PDo0
Output
Mux &
Drivers
PDo7
4
CTo0-3
PDi0
PDi7
PCKR
PCKT
Timing
RES
Control
PPFRi
PPFTi/o
Unit
F0i/o
streams (512
Multiple Pages of 512 Position
8
TX Path Data Memory
16
2430 Position
TX Path
Connection Memory
8
8
Multiple Pages of 2430-Byte
RX Path Data Memory
15
512 Position
RX Path
Connection Memory
CPU Interface
Figure 1 - Functional Block Diagram
Distributed Hyperchannel Switch
Preliminary Information
Ordering Information
MT90840AL
100 Pin PQFP
MT90840AP
84 Pin PLCC
-40 C to 85 C
•
Diagnostic alarm functions and clock
phase-status word for clock monitoring
•
IEEE 1149 (JTAG) boundary scan port
Applications
•
Bridging ST-BUS/MVIP buses to high speed
Time Division Multiplexed backplanes at
SONET rates (STS-1, STS-3)
•
High speed isochronous backbones for
distributed PBX and LAN systems
•
Switch platforms of up to 2430 channels with
guaranteed frame integrity for wideband
channels
•
Serial bus control and monitoring
•
Data multiplexing
•
High speed communications interface
Serial
8
Bidirectional
to
Parallel
&
Parallel
to
Serial
Bidirectional
8
Conver-
ters
Internal
Registers
MT90840
ISSUE 2
March 1997
STi0
I/O
Driver
STi7
STo0
I/O
Driver
STo7
5
JTAG
TEST
Pins
8
8
2-231
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Related Manuals for Mitel MT90840
Summary of Contents for Mitel MT90840
- Page 1 MT90840 Distributed Hyperchannel Switch Preliminary Information Features ISSUE 2 March 1997 • Time slot interchange function between eight Ordering Information pairs of ST-BUS/GCI/MVIP streams (512 MT90840AL 100 Pin PQFP channels) and parallel data port MT90840AP 84 Pin PLCC • Programmable data rates on the parallel port -40 C to 85 C (19.44, 16.384, or 6.480 Mbyte/s) •...
- Page 2 MT90840 Preliminary Information STi0 STo0 STi1 STo1 STi2 STo2 STi3 STo3 STi4 STo4 STi5 STo5 STi6 STo6 STi7 STo7 C4/8R1 SPCKo 84 PIN PLCC F0i/o C4/8R2 TRST CTo3 CTo2 PPFRi CTo1 PCKT CTo0 PCKR PDo7 PDo6 PDo5 PDo4 PDo3 PDo2 PDo1 AS/ALE PDo0...
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Page 3: Pin Description
MT90840 Preliminary Information Pin Description Pin # Name Description DS/RD Data Strobe/Read (Input). In Motorola multiplexed-bus mode this pin is DS, an active high input which works with CS to enable read and write operation. In Intel/ National multiplexed-bus mode this pin is RD, an active low input which enables a read-cycle and configures the data bus lines (AD0-AD7) as outputs. - Page 4 MT90840 Preliminary Information Pin Description (continued) Pin # Name Description F0i/o Serial Port Frame Synchronization (Bidirectional). This 8 kHz frame pulse signal indicates the TDM 125 sec frame boundary on the serial data port. This pin is compatible with both ST-BUS/MVIP and GCI formatted framing signals. In TM1 this pin is an input, and the MT90840 senses the polarity of this frame pulse and automatically adapts the serial data port timing to the applicable format (ST-BUS or GCI).
- Page 5 MT90840 Preliminary Information Pin Description (continued) Pin # Name Description TRST Test Reset (Input). Asynchronously initializes the JTAG TAP controller, placing it in the Test-Logic-Reset state. This pin is pulled high internally when not driven. This pin should be pulsed low on power-up, or held low continuously, to ensure that the MT90840 is in the normal functional state, and not the test state.
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Page 6: Functional Description
• the microprocessor (CPU) interface, device. The MT90840 bridges serial-bus telecom • the test interface (JTAG). components, using the Mitel ST-BUS or other industry-standard serial buses, onto a higher speed “backbone”. Mixed data, voice and video signals can The MT90840 supports four major timing/switching... - Page 7 MT90840 Preliminary Information Frame Boundary Established by F0 C4/8R1&2 (4 MHz) Serial I/O Ch. 31 Bit 1 Ch. 31 Bit 0 Ch. 0 Bit 6 Ch. 0 Bit 7 2 Mbps Serial I/O Ch. 63 Bit 2 Ch. 63 Bit 1 Ch.
- Page 8 MT90840 Preliminary Information an address-value in the path’s Data Memory. A given The Rx Path Connection Memory is programmed, for output time slot is controlled by programming the each output time slot, with the address-value of the Connection Memory control-address with source channel to be read out of the Rx Path Data address-value of the source input time slot.
- Page 9 MT90840 Preliminary Information programmed to switch parallel inputs to parallel specific time slot in an output stream (e.g. outputs. each parallel output channel STo0-channel7) is programmed in the Rx Path control-address, the Tx Path Connection Memory is Connection Memory as an input, the corresponding programmed with the 12-bit address-value of the time slot on the equivalent input stream (i.e.
- Page 10 MT90840 Preliminary Information Register enables the internal divider, and the SPCKo Data Input Port (PDi0-7), a Receive Frame sync output (and internal 4.096 MHz clocks) are driven by signal (PPFRi) and a Transmit Frame sync signal the clock divided-down from PCKR. At 16.384 MHz, (PPFT), and Transmit (PCKT) and Receive (PCKR) this is a simple divide-by-4, and the SPCKo output Clocks.
- Page 11 MT90840 Preliminary Information streams, and trigger the PPCE interrupt bit. PPCE • TM4/Parallel Switching: 2430 (or 2048) channel will be triggered by PPFRi moving from the expected switching from PDi to PDo. time, but PPCE will not be triggered by a missing The TM1-0 bits in the TIM Register are used to PPFRi.
- Page 12 MT90840 Preliminary Information TM1. This allows for flexible round-trip data delays in Multiple-MT90840 sub-mode star or ring type networks. An elastic buffer on the available for operation at 6.48 Mbyte/s. receive parallel port compensates for the difference in phase between PPFRi/PCKR and F0i/C4. The Timing Mode 2 (TM2) - Ring Slave elastic buffer can also tolerate up to 50 sec +/- 25 sec) of clock drift and jitter before the buffer...
- Page 13 MT90840 Preliminary Information The transmit path does not provide an elastic buffer, output is not used at 8.192 MHz). The serial port and therefore the serial port clock must be tightly frame pulse (F0o) will be slaved to the parallel port locked (in frequency) to the parallel port clock frame pulse (PPFRi), and will be clocked out by (PCKR).
- Page 14 MT90840 Preliminary Information MT90840 8 kHz TX STi/o 0-7 SFDI = 0 PPFT STi0-7 Data TX STi/o 0-7 PDo0-7 ST-BUS STo0-7 TX/RX Clock Components PCKR 4.096 MHz Data RX SPCKo PDi0-7 8 kHz 8 kHz 8 kHz RX PPFRi C4/8R1 & 2 Source 4.096 MHz or 8.192 MHz...
- Page 15 MT90840 Preliminary Information Clock Reference Parallel Data Out MT90840 Parallel Data In PDo0-7 PDi0-7 TX 8 kHz REF PPFTo 8 kHz RX 8 kHz PPFRi Source PCKR 19.44 or 16.384 MHz (RX) Figure 8 - Timing Mode 4 Configuration Timing Mode 4 (TM4) - Parallel Data Switching these per-channel features are Bypass, Control Outputs, Output Enable, and Message Mode.
- Page 16 MT90840 Preliminary Information Mode Data Rates Minimum Delay Total Throughput Delay TM1, TM2, Dmin = 7.7 sec D = Dmin + 1 frame + Po - Si = 132.7 sec + Po - Si or TM3 S/P Note 1 Min. 7.7 sec, Avg. 133 sec, Max. 258 sec TM1P/S Dmin = ELDmin D = 1 frame + ELD + So - Pi = 125 sec + ELD + So - Pi...
- Page 17 MT90840 Preliminary Information Output Frame Boundary Established by PPFT PPFT PDo7-0 Channel 2428 Channel 2429 Channel 1 Channel 0 Byte Timing CTo0-3 TPCM High, CTn bit TPCM High, CTn bit TPCM High, CTn bit TPCM High, CTn bit Outputs address 2429 address 0 address 1 address 2428...
- Page 18 MT90840 Preliminary Information all 16 serial streams can be individually controlled, so that up to 512 channels can be either transmitted Serial Input TPDM Channel Address or received. As an example, if all DC bit locations of CPU Port Addressing: RPCM High are set HIGH, all 512 channels on STi0, Ch0 000H...
- Page 19 MT90840 Preliminary Information mode. Each of the 512 output channels has a TPDM control-address in the RPCM. CPU accesses require Serial I/O Address Channel the 2 LSBs of the CAR Register, and the 7 LSBs of the address bus. Per-channel direction control in this STi0, Ch0 000H CPU Port Addressing:...
- Page 20 MT90840 Preliminary Information Note that if the parallel port clocks PCKR & PCKT or Serial Input TPDM serial port clocks C4/8R1 & C4/8R2 are not present Channel Address during an internal memory access, the DTA output signal may be held HIGH until the clocks are applied STi0, Ch0 000H CPU Port Addressing:...
- Page 21 MT90840 Preliminary Information Reset Value Type LOCATION (Hex) IMS Register Control Register TIM Register GPM Register ALS Register Test (leave 00hx) reserved reserved Phase Status (Low byte) Phase Status (High 3 bits) reserved Table 2 - MT90840 Register Address Mapping short, or a signal contention, prevents the DTA pin address pin AD7 HIGH to indicate a memory access.
- Page 22 MT90840 Preliminary Information the DTA pin will be asserted (as the data is stored in Clock Quality and TM2 RPCM Access Integrity the write-pipeline) but the next CPU access will not In Timing Mode 2 the serial frame pulse F0o must be see DTA asserted.
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Page 23: Jtag Support
MT90840 Preliminary Information DR1-0 and FDC in the IMS register) before Timing Mode Initialization programming the RPCM. On system power-up, the CPU should program the b) The GPM Register is written. The CPU sets the MT90840 IMS, GPM, and TIM registers to establish Block-Programming Enable (BPE) bit to HIGH the data rates, the Timing Mode (1,2,3,4), and the and the Block-Programming Data (BPD7-4) bits... - Page 24 MT90840 Preliminary Information I/O pin of the IC. The operation of the boundary-scan • The Test Data Output (TDO) circuitry is controlled by a Test Access Port (TAP) Serial data is shifted out on this pin. Depending Controller. on the present mode of the TAP controller, data will come from one of: the instruction register, the boundary scan register or the bypass Test Access Port (TAP)
- Page 25 4:11 pdi<0:7>_in 106:107 spcko_en, spcko_out 12:14 ppft_en, ppft_out, ppft_in Table 4 - Boundary Scan Register 15:22 pdo<0:7>_out Please visit our web site at www.semicon.mitel.com to download a BSDL file for the MT90840. pdo_en enables pdo<0:7 >outputs 24:27 cto<0:3>_out always enabled...
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Page 26: Register Description
MT90840 Preliminary Information Register Description Interface Mode Selection Register (IMS) - READ/WRITE PPS1 PPS0 DR1-0 Serial Port Data Rate Selection. Select one of three different data rates at the serial inputs and outputs of the MT90840. DR1 DR0 Data Rate 2.048 Mbps 4.096 Mbps 8.192 Mbps... - Page 27 MT90840 Preliminary Information General Purpose Mode Register (GPM) - READ/WRITE BPD7 BPD6 BPD5 BPD4 PPFP SPFP BPD7-4 Block-Programming Data bits 7-4. These bits carry the value to be loaded into the TPCM-High or RPCM-High memory when the Memory Block-Programming feature is activated. When BPE is set HIGH, the contents of bits BPD7-4 are loaded into the four most significant bits of TPCM-High or RPCM-High, and the four least significant bits of TPCM-High or RPCM-High are zeroed.
- Page 28 MT90840 Preliminary Information Control Register (CR) - READ/WRITE SEL2 SEL1 SEL0 HA11 HA10 This register selects which 128 byte page of which internal memory will be accessed by the CPU when the address bit AD<7> is high. (When address bit AD<7> is low, the control registers are accessed.) SEL2-0 Memory Select bits.
- Page 29 MT90840 Preliminary Information Internal Memory Description Transmit Path Connection Memory High (TPCM High) - This is an 8-bit x 2430-position memory. CTo2/ CTo3/ (TX Path CM High) PPBY CTo1 CTo0 AB10 AB11 OE/CTo0 Output Enable. Provides per channel tristate control on the parallel port side. It controls the MT90840 parallel output drivers to disable (tristate, when LOW) or enable (when HIGH) the transmission of data from the device.
- Page 30 MT90840 Preliminary Information Receive Path Connection Memory High (RPCM High) - This is a 7-bit x 512-position memory. Used only in TM1, 2, & 3. AB11 AB10 (RX Path CM High) Message Channel: The message channel contents are provided by the CPU in bits AB0-7 in the Rx Path Connection Memory Low.
- Page 31 MT896x ST-BUS Filter/Codec MT90810 FMIC Filter/Codec MT8930 / 71 ST-BUS (2B+D) I/F MT8985/6 ISO Ethernet SERVER LAN ADAPTER CARD Interchassis Signalling (e.g. Mitel’s Connection Master Software) Figure 16 - CTI Distributed Architecture Implemented with the MT90840 2-261...
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Page 32: Absolute Maximum Ratings
MT90840 Preliminary Information synchronization scheme may be used in applications all or part of the received input parallel data to be such as the proposed MVIP multi-chassis level 3 bypassed to the output parallel port feeding the ring interface (MC-3 system) utilizing point-to-point or back with the data which is not destined for the local point-to-multipoint switching connections. -
Page 33: Ac Electrical Characteristics
MT90840 Preliminary Information AC Electrical Characteristics - Voltages are with respect to ground (V ) unless otherwise stated. ‡ Characteristics Units Test Conditions 1 C4/8 Input - Clock Period: C4/8R1 or C4/8R2 4.096 MHz (2.048 & 4.096 Mbps) 8.192 MHz (8.192 Mbps) SPCKo Output - Clock Period from 19.44 MHz 60/40% internal divider (2.048 &... - Page 34 MT90840 Preliminary Information AC Electrical Characteristics - Voltages are with respect to ground (V ) unless otherwise stated. ‡ Characteristics Units Test Conditions 10 STo Delay from High-Z to Active =30pF, R 2.048 and 4.096 Mbps (TM2 &TM3) 2.048 and 4.096 Mbps (TM1) 8.192 Mbps (STio0-3) 11 STo Output Delay from SPCKo =30pF...
- Page 35 MT90840 Preliminary Information Foi input (8 kHz) clkh clkl C4/8R1 (4.096 MHz) stis stih STi0-7 bit 0, ch. 31 bit 7, ch. 0 bit 0, ch. 31 bit 7, ch. 0 STo0-7 Serial Port with Negative Polarity F0 (ST-BUS) clkh clkl C4/8R1 (4.096 MHz)
- Page 36 MT90840 Preliminary Information F0ooutput (8 kHz) clkh clkl SPCKo (4.096 MHz) stis stih STi0-7 bit 0, ch. 31 bit 7, ch. 0 STo0-7 bit 0, ch. 31 bit 7, ch. 0 Serial Port with Negative Polarity F0 (ST-BUS) clkh clkl SPCKo (4.096 MHz) STo0-7...
- Page 37 MT90840 Preliminary Information clkh clkl C4/8R1 (4.096 MHz) STo0-7 bit 7, ch. 0 bit 0, ch. 63 bit 6, ch. 0 stis stih STi0-7 bit 7, ch. 0 F0i input (8 kHz) Serial Port with Negative Polarity F0 (ST-BUS) clkh clkl C4/8R1 (4.096 MHz)
- Page 38 MT90840 Preliminary Information clkh clkl SPCKo (4.096 MHz) STo0-7 bit 7, ch. 0 bit 0, ch. 63 bit 6, ch. 0 stis stih STi0-7 bit 7, ch. 0 F0o output (8 kHz) F0 Frame Sync with Negative Polarity (SPFP = 0) clkh clkl SPCKo...
- Page 39 MT90840 Preliminary Information clkh clkl C4/8R1 (8.192 MHz) STo0-7 bit 7, ch. 0 bit 6, ch. 0 bit 0, ch.127 stis stih STi0-7 bit 7 F0i input (8 kHz) Note: Polarity of F0i is automatically detected in TM1. Expected polarity of F0i in TM2 (SFDI=1) must be programmed with SPFP bit in GPM register. Figure 22 - Serial Port Timing for 8.192 Mbps - TM1 and TM2 (SFDi = 1) C4/8 (GCI)
- Page 40 MT90840 Preliminary Information clkh clkl C4/8R1** (8.192 MHz reference) STo0-7 bit 7, ch. 0 bit 0, ch.127 bit 6, ch. 0 stis stih bit 7 STi0-7 F0o output (8 kHz) Frame Sync with Positive Polarity (SPFP = 1) clkh clkl C4/8R1** (8.192 MHz reference)
- Page 41 MT90840 Preliminary Information TCP controls the clock-edge PCKT/PCKR on which the output changes. byte m-1 byte m+1 byte m PDo0-7 TCP = 1 CTo corresponding to CTo corresponding to byte m byte m+1 CTo0-3 PCKT/PCKR byte m-1 byte m+1 byte m PDo0-7 TCP = 0 CTo corresponding to...
- Page 42 MT90840 Preliminary Information clkh clkl PCKR stis stih Byte 1 Byte 0 PDi0-7 PPFRi Figure 28 - Parallel Port Receive Timing AC Electrical Characteristics - Parallel Data Port ‡ Characteristics Units Test Conditions PCKT/PCKR clock period PCKT/PCKR HIGH time clkh PCKT/PCKR LOW time clkl PPFTo output delay...
- Page 43 MT90840 Preliminary Information PCKR PPFRi PPFT TCP = 0 TCP = 1 PPFT Note: For the PPFT depicted above, PPFP = HIGH. If PPFP is LOW, the PPFT line will have negative pulse polarity. Figure 29 - Parallel Port in Timing Mode 4 STo (4 Mbps) Ch.
- Page 44 MT90840 Preliminary Information † AC Electrical Characteristics - Intel/National- HPC Multiplexed Bus Mode Voltages are with respect to ground (V ) unless otherwise stated. Test Conditions/ ‡ Characteristics Units Notes 1 ALE pulse width 2 Address setup from ALE falling 3 Address hold from ALE falling 4 RD Active after ALE falling alrd...
- Page 45 MT90840 Preliminary Information 2.0V 0.8V 2.0V AD0- ADDRESS DATA 0.8V alrd csrw 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V alwr 2.0V 0.8V Figure 32 - Intel/National Multiplexed Bus Timing 2-275...
- Page 46 MT90840 Preliminary Information † AC Electrical Characteristics - Motorola Multiplexed Bus Mode Voltages are with respect to ground (V ) unless otherwise stated. Test Conditions/ ‡ Characteristics Units Notes AS pulse width Address setup from AS falling Address hold from AS falling Data setup from DTA LOW on =150 pF on DTA, read...
- Page 47 MT90840 Preliminary Information 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V AD0-7 ADDRESS DATA 0.8V 2.0V AD0-13 ADDRESS DATA 0.8V 2.0V 0.8V 2.0V 0.8V Figure 33 - Motorola Multiplexed Bus Timing 2-277...
- Page 48 MT90840 Preliminary Information mssu tclk disu tclkl tclkh trst TRST Figure 34 - Boundary Scan Test Port Timing AC Electrical Characteristics - Boundary-Scan Test Port and RESET Pin Parameter Symbol Units Test Conditions TCK period width tclk TCK period width LOW tclkl TCK period width HIGH tclkh...
- Page 49 MT90840 Preliminary Information 0.165 0.200 (4.20) (5.08) 0.090 0.130 (2.29) (3.30) 0.185 1.195 (30.10) (30.35) 1.150 1.158 (29.210) (29.413) 1.090 1.130 (27.69) (28.70) 0.026 0.032 (0.661) (0.812) 0.013 0.021 (0.331) (0.533) 0.050 BSC (1.27 BSC) 0.020 (0.51) Notes: 1) Not to scale. 2) Governing dimensions are in millimeters ().
- Page 50 MT90840 Preliminary Information Notes: 2-280...