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Preliminary Information
PPFT
PDo7-0
Channel 2428
Byte Timing
CTo0-3
TPCM High, CTn bit
Outputs
address 2428
Note: For applications at 16.384 and 6.48 Mbyte/s, only 2048 and 810 positions are usable, in the TPCM.
STi0
O/P
. . . . .
0
1
2
3
Figure 10 - Balanced Per-Channel Serial Direction Control as Determined by DC Bit
TPCM High location is output on the corresponding
CTo pin once every frame. See Figure 9. The control
outputs can be used to control other devices, such
as buffers, to allow sharing of the parallel port data
bus.
Per-channel Tri-state (Serial and Parallel)
The MT90840 provides per-channel tri-state of the
output pins on both the serial and parallel port. The
OE bit in each address of the TPCM and RPCM
determines if data will be driven during a particular
time slot, or if the pin will be placed in a
high-impedance state during that time slot. The OE
bit overrides all other per-channel control bits.
Per-channel Message Mode (Serial and Parallel)
The MT90840 provides per-channel message mode
capability on both the serial and parallel port. The
MC bit in each address of the TPCM and RPCM
determines if the Connection Memory Low byte is to
be used as an address, or as data to be output on
the particular channel (message mode). When the
MC bit is HIGH, the Connection Memory Low byte is
used as message data. As well as driving message
data on the serial (RPCM) and parallel (TPCM)
ports, the MT90840 allows the CPU to read serial or
parallel data channels from the TPDM or RPDM.
Applications for message mode include digital
silence, proprietary signalling, and creating fixed 8
kHz framing patterns.
Output Frame Boundary Established by PPFT
Channel 2429
TPCM High, CTn bit
address 2429
Figure 9 - Parallel Port Control Outputs, CTo0-3
DC=0 for STo 0 channel 1
I/P
MT90840
29
30
31
DC=1 for STo 0 channel 29
Channel 0
TPCM High, CTn bit
address 0
I/P
0
1
2
3
Per-channel Direction Control on the Serial Port
The MT90840 provides the ability to use any nominal
output serial channel as an input or as an output.
The direction of each output serial channel is
controlled by the DC bit in the appropriate byte of the
Receive Path Connection Memory High (RPCM
High). When DC is HIGH the matching channel is an
output. The per-channel direction control feature of
the MT90840 can be activated in one two modes:
balanced, or add/drop operation.
•
Balanced Operation (all serial data rates)
This mode is enabled when the FDC bit in the IMS
Register is LOW. In this mode, each of the DC bits
controls two serial channels: the nominal output and
the nominal input. If a channel on a nominal output
serial stream (STo0-7) is re-defined as an input, the
same-number channel on the matching input stream
(STi0-7) will be defined as an output. For example, if
channel 0 on STo7 is programmed as an input
(DC=0), then channel 0 on STi7 is defined as an
output. Each DC-bit's state controls the direction of a
channel on the nominal output stream (DC is HIGH
for output), and inverse-sense controls a channel on
the nominal input stream (DC is LOW for output).
This is shown in Figure 10.
•
Add/Drop Operation (2.048 Mbps only)
This mode is enabled when the FDC bit in the IMS
Register is HIGH. In Add/Drop mode all channels on
MT90840
Channel 1
TPCM High, CTn bit
address 1
STo0
O/P
. . . . .
29
30
31
2-247
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