Address Decorder And Bank Register - Epson L-1000 Technical Manual

REV.-A
2.2.4 Address Decoder and Bank Register
This section describes the address decoder and bank register.
Address Decoder
This unit includes an address decoder in gate array E01A05KA (6C). The address decoder outputs a chip-select
signal to the internal PROM (3C), external PROM, 4MCG (5C), 1 MCG (2C), external CG, RAM (2C), HEAD gate
array (7A) via address lines AB12 through AB15 and bank lines 7 and 6 (in the gate array). However, the chip
select for the CS is generated in conjunction with the RD signal, and that of the RAM is generated in conjunction
with the ALE signal.
Software control of firmware can check whether an external PROM is mounted or not, and if the correct PROM
is mounted, the memory map shown in Figure 2-31 is obtained by writing bit 7 LOW at address FOOl hex.
LQ-500I L-1000
Figure 2-31. Memory Map
PRINCIPLES OF OPERATION
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