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4.12 PARALLEL INPUT CIRCUIT
This port is used as being shared by PCI (0 7), 8-bit parallel general purpose input. STB input, ACK output and
BUSY output are used as independent ports.
When STB input is made "low", PCI port data are latched. Also, at the same time, BUSY output is made "high".
With STB input returned to "high", INTR pin gets "low" and latching of data in the input port is notified to CPU. It
can be used as the data reading request signal. BUSY and INTR are reset in the timing with which CPU reads PCI
port data, where, at the same time, ACK signal is also output.
When you do not use this function, keep STB pin in "low". Then, it can be used as a general purpose 8-bit input port
(PCI).
BUSY output is available in timings other than those listed above. With data written in PCO7 (bit 7 of XX04h
address) port, BUSY output is available.
For other outputs, use other ports.
4.13 ADDRESS LATCH CIRCUIT
This port is used as shared by the 8-bit parallel type of general purpose output PAO (0
uses address bus and data bus by multiplexing.
Perform address latching at the fall edge where ASTB input is made "low". When you do not use this function, keep ASTB pin at
"low". Then, it can be used as a general purpose 8-bit output port (PAO).
MIN
T1
100
T2
100
T3
100
T4
-
T5
-
T6
-
16
MAX
UNIT
-
ns
-
ns
-
ns
80
ns
80
ns
80
ns
7). This is applicable to CPU which
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