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4.6
INTERNAL ADDRESS MAP
A3
A2
A1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
1
X
X
1
X
X
X
X
X
X
X
X
X mark indicates either "0" or "1".
Ports other than those listed above are subject to independent operation.
A0
RD
HWR
CS1 OPERATION AND APPLICABLE PORT
0
0
1
0
0
1
0
0
1
0
1
0
1
1
0
0
0
0
1
0
0
1
0
0
1
0
1
0
1
1
0
0
0
0
1
0
0
1
0
0
1
0
1
0
1
1
0
0
0
0
1
0
0
1
0
0
1
0
1
0
1
1
0
0
X
0
1
0
X
1
0
0
X
X
X
1
X
1
1
0
Prohibited
Print data buffer
Prohibited
DMA request
PAI port input
PA0 port output & address latch output
PBI port input
Prohibited
PCI port input & Centro-data input
PC0 port output (PBUSY)
180° turning output
Bit data buffer for processing
Double width lower 8-bit output
Double width upper 8-bit output
Head control mode register
90 °turning output
90 °turning data buffer
Data bus high impedance
Data bus high impedance
11
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