Table 3-18. Ide Signal Descriptions - Ampro COM 830 Reference Manual

Chapter 3
Table 3-17. PCI Signal Descriptions (Continued)
PCI_TRDY#
PCI_STOP#
PCI_PAR
PCI_PERR#
PCI_REQ[0:3]#
PCI_GNT[0:3]#
PCI_RESET#
PCI_LOCK#
PCI_SERR#
PCI_PME#
PCI_CLKRUN#
PCI_IRQ[A:D]#
PCI_CLK
PCI_M66EN

Table 3-18. IDE Signal Descriptions

IDE Description
IDE_D[0:15] Bidirectional data to / from IDE device.
IDE_A[0:2] Address lines to IDE device.
IDE_IOW# I/O write line to IDE device. Data latched on
trailing (rising) edge.
COM 830
PCI bus Target Ready control line, active low
PCI bus STOP control line, active low, driven
by cycle initiator
PCI bus parity
Parity Error: An external PCI device drives
PERR# when it receives data that has a parity
error.
PCI bus master request input lines, active low.
PCI bus master grant output lines, active low.
PCI Reset output, active low.
PCI Lock control line, active low.
System Error: SERR# may be pulsed active
by any PCI device that detects a system error
condition.
PCI Power Management Event: PCI
peripherals drive PME# to wake system from
low-power states S1–S5.
Bidirectional pin used to support PCI clock
run protocol for mobile systems.
PCI interrupt request lines.
PCI 33MHz clock output.
Module input signal indicates whether an
off-module PCI device is capable of 66MHz
operation. Pulled to GND by Carrier Board
device or by Slot Card if the devices are NOT
capable of 66MHz operation.
If the module is not capable of supporting
66MHz PCI operation, this input may be a
no-connect on the module.
If the module is capable of supporting 66MHz
PCI operation, and if this input is held low by
the Carrier Board, the module PCI interface
shall operate at 33MHz.
Reference Manual
Signals and Pinout Tables
I/O PU 8k2
3.3V 3.3V
I/O PU 8k2
3.3V 3.3V
I/O
3.3V
I/O PU 8k2
3.3V 3.3V
I 3.3V PU 8k2
3.3V
O 3.3V
O 3.3V
I/O PU 8k2
3.3V 3.3V
I/O PU 8k2
3.3V 3.3V
I PU 10k
3.3VS 3.3VSB
B
I/O PU 8k2
3.3V 3.3V
I 3.3V PU 8k2
3.3V
O 3.3V
I Not
connected
I/O PU/PD Comment
I/O
3.3V
O 3.3V
O 3.3V
39