Multi-Level Caches; Quickpath Interconnect Controller - HP ProLiant DL160se - G6 Server Introduction Manual

Multi-level caches

Xeon 5500 Series processors have a three-level cache hierarchy (Figure 1):
• An on-core, 64-kilobyte, Level 1 cache, split into two 32 kilobyte caches: one for data and one for
instructions
• 256-kilobyte, Level 2 cache for each core to reduce latency
• A Level 3 cache of up to 8 megabytes shared by all cores
Figure 1. Block diagram of three-level cache hierarchy for Intel Xeon 5500 Series processors
The Level 3 cache is shared and inclusive, which means that it duplicates the data stored in the Level
1 and Level 2 caches of each core. This guarantees that data is stored outside the cores and
minimizes latency by eliminating unnecessary core snoops to the Level 1 and Level 2 caches. Flags in
the Level 3 cache track which core's cache supplied the original data. Therefore, if one core modifies
another core's data in Level 3 cache, the Level 1 and Level 2 caches are updated as well. This
eliminates excessive inter-core traffic and ensures multi-level cache coherency.

QuickPath Interconnect controller

Xeon 5500 Series processors attain their performance potential through the Intel QuickPath
Architecture (Figure 2); high-speed, point-to-point interconnects directly connect the processors with
each other. The Intel QuickPath architecture also connects each processor to distributed shared
memory and to the I/O chipset.
Each QuickPath Interconnect consists of two unidirectional links that operate simultaneously in each
direction using differential signaling. Unlike a typical serial bus, the QuickPath interconnects transmit
data packets in parallel across multiple lanes and packets are broken into multiple parallel transfers.
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