Dynamic Cpu Phase Shedding; Managing Processor Technologies; Quickpath Interconnect Power; Disabling Processor Cores - HP ProLiant DL160se - G6 Server Introduction Manual

Dynamic CPU phase shedding

On entry into a low power state (less than 20 W), the Intel Xeon 5500 Series processors will activate
the Power Status Indicator (PSI). When PSI is engaged, ProLiant G6 servers turn off voltage regulator
phases, thereby saving power and increasing power efficiency.

Managing processor technologies

QuickPath Interconnect power

The Xeon 5500 Series processor lets the QuickPath Interconnect (QPI) buffers enter a sleep state to
reduce power requirements when the QPI links are not active. HP enables this Intel feature for G6
servers through BSU. Once this feature is enabled, the Intel processor determines when to put the QPI
buffers into a sleep state. It appears that QPI power management has no measureable impact on
performance.

Disabling processor cores

Through BSU, administrators can disable one or more cores in the Xeon 3400 and 5500 Series
processors (per physical processor). When enabled, the command will apply to all physical
processors in the server. Engaging this capability saves power and has the potential to improve
performance in servers running single workloads or applications with low threading requirements.

C-state package limit setting

The Xeon 3400 and 5500 Series processor supports C-states for each core within the processor. C-
states define the power state of system processors and are an open specification of the ACPI group.
The micro-architecture of the Xeon 5500 Series processors supports processor C-states C0, C1, C3,
and C6. C-state C0 represents a fully active core that is executing instructions. The other C-states
represent further power reduction levels for idle cores. The micro-architecture of the Xeon 3400 Series
processor supports processor C-states C1e, C3, and C6. Any core within the processor can change
C-states independently from the other cores.
Parameters for the maximum C-state allowable for an idle processor are set through the BSU and
initiated by the OS. The higher the C-state allowed at idle, the more power savings, but only at idle.
Also, the higher the C-state, the higher the latency involved when the core returns to activity.

Managing memory technologies

Memory channel interleaving

As described in the memory section, the alternate routing used for channel interleaving decreases
memory access latency and increases performance.
Memory interleaving is configured in the BSU. Disabling memory channel interleaving makes access
to contiguous memory addresses revert to one channel. Single-channel access degrades performance,
but makes it possible for the memory controller to place less frequently accessed DIMMs into a low
power state which saves power. Memory interleaving can have a negative performance effect based
on the application load of the server. Administrators should perform testing in their application
environment to determine the trade-off between power savings and performance.

Maximum memory data rates

The maximum memory data rate is effectively 1333 MHz for ProLiant G6 Intel platforms. Depending
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on the memory configuration and the processor that is installed, the system may automatically reduce
the Quick Path Interconnect speed. While the "Auto" setting (which equates to 1333 MHz) is the
default setting, users have the option to manually lower the effective data rates to 1066 MHz or 800
6 The memory operates in a double-pumped manner so that the effective bandwidth is double the physical clock rate of the
memory. Mega-transfers/second describes the data rate.
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