IBM NetVista Technical Information Manual page 58

Table 34. DMA I/O address map
000E
000F
0081
0082
0083
0087
0089
008A
008B
008F
00C0
00C2
00C4
00C6
00C8
00CA
00CC
00CE
00D0
00D2
00D4
00D6
00D8
00DA
00DC
00DE
00DF
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NetVista™ Technical Information Manual
Address
(hex)
Channels 0-3, clear mask register (write)
Channels 0-3, write all mask register bits
Channel 2, page table address register
Channel 3, page table address register
Channel 1, page table address register
Channel 0, page table address register
Channel 6, page table address register
Channel 7, page table address register
Channel 5, page table address register
Channel 4, page table address/refresh register
Channel 4, memory address register
Channel 4, transfer count register
Channel 5, memory address register
Channel 5, transfer count register
Channel 6, memory address register
Channel 6, transfer count register
Channel 7, memory address register
Channel 7, transfer count register
Channels 4–7, read status/write command register
Channels 4–7, write request register
Channels 4–7, write single mask register bit
Channels 4–7, mode register (write)
Channels 4–7, clear byte pointer (write)
Channels 4–7, master clear (write)/temp (read)
Channels 4–7, clear mask register (write)
Channels 4–7, write all mask register bits
Channels 5–7, 8- or 16-bit mode select
Description
Byte
Bits
pointer
00 – 03
00 – 03
00 – 07
00 – 07
00 – 07
00 – 07
00 – 07
00 – 07
00 – 07
00 – 07
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 07
00 – 02
00 – 02
00 – 07
00 – 07
00 – 03
00 – 03
00 – 07