Intel Desktop Board D915GEV/D915GRF Technical Product Specification
Table 15.
PCI Interrupt Routing Map
PCI Interrupt Source
IEEE-1394a controller
PCI bus connector 1
PCI bus connector 2
PCI bus connector 3
PCI bus connector 4
NOTE
In PIC mode, the ICH6 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6,
7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a
unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or
more of the PIRQ lines to be connected to the same IRQ signal. Refer to Table 14 for the
allocation of PIRQ lines to IRQ signals in APIC mode.
PCI interrupt assignments to the USB ports, Serial ATA ports, and PCI Express ports are dynamic.
58
ICH6 PIRQ Signal Name
PIRQA
PIRQB
PIRQC
INTA
INTD
INTC
INTA
INTB
PIRQD
PIRQE
PIRQF
INTD
INTA
INTC
INTB
INTB
INTA
INTC
PIRQG
PIRQH
INTB
INTC
INTA
INTD
INTD
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