TYAN TOMCAT I815E Manual page 40

Chapter 3
BIOS Configuration
System Mem ory Frequency Sets frequency of onboard DIMM memory. [Default is
SDRAM Refresh
DRAM Cycle Tim e (SCLKs)
CAS Latency (SCLKs)
RAS# to CAS# Delay (SCLKs) Sets length of delay inserted betw een the RAS and CAS
RAS# Precharge (SCLKs)
DRAM Page Closing Policy
Mem ory Hole
If the Init Display Cache Memory is enabled, the following options will appear.
Paging Mode Control Enable / disable paging mode. [Default is Closed ]
RAS-to-CAS Override Sets delay override. [Default is Disabled ]
CAS Latency
RAS Tim ing
RAS Pre-charge
Auto ]
Sets interval betw een Refresh signals to SDRAM. [Default
is Auto ]
Sets length of DRAM cycle time in SCLKs. [Default is Auto ]
Sets number of SCLKs betw een time w hen the Read
command is sampled by DRAM, and the Whitney Sample
reads data from SDRAM. [Default is Auto ]
signals of the DRAM system memory access cycle if
SDRAM is installed. [Default is Auto ]
Sets length of RAS precharge part of DRAM system
memory access cycle w hen SDRAM system memory is
installed. [Default is Auto ]
Sets w hether DRAM pages should be closed after use, or
left open. [Default is Open ]
Sets the location of an area of memory that cannot be
address on the ISA bus. [Default is Disabled ]
Sets number of SCLKs betw een the time w hen Read
command is sampled by DRAM and the Whitney Sample
reads data from SDRAM. [Default is Slow ]
Sets clock frequency for RAS and RC. [Default is Slow ]
Sets clock frequency for RAS and RP. [Default is Slow ]
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