Pwok (Power Ok) Output Signal; Figure 41. Pson# Required Signal Characteristic; Table 44. Pwok Signal Characteristics - Intel SR1475 Technical Product Specification

Intel® Server Chassis SR1475 / Intel® Server System SR1475NH1-E
0.3V ≤ Hysteresis ≤ 1.0V
in 1.0-2.0V input voltage range is required
Disabled
Enabled
0V

6.38 PWOK (Power OK) Output Signal

PWOK is a power OK signal and will be pulled HIGH by the power supply to indicate that all the
outputs are within the regulation limits of the power supply. When any output voltage falls below
regulation limits or when AC power has been removed for a time sufficiently long so that power
supply operation is no longer guaranteed, PWOK will be de-asserted to a LOW state. The start
of the PWOK delay time shall inhibited as long as any power supply output is in current limit.
PWOK = High
PWOK = Low
Logic level low voltage, Isink=4mA
Logic level high voltage, Isource=200μA
Sink current, PWOK = low
Source current, PWOK = high
PWOK delay: T
pwok_on
PWOK rise and fall time
Power down delay: T
Revision 1.0
≤ 1.0 V PS is
enabled
1.0V

Figure 41. PSON# Required Signal Characteristic.

Table 44. PWOK Signal Characteristics

Signal Type
pwok_off
≥ 2.0 V PS is
disabled
2.0V
Open collector/drain output from power supply. Pull-up
to VSB located in system.
Power OK
Power Not OK
MIN
0V
2.4V
100ms
1ms
5.25V
MAX
0.4V
5.25V
4mA
2mA
1000ms
100μsec
200msec
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