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Infineon Manuals
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XC866
User manual
Infineon XC866 User Manual
8-bit single chip microcontroller
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
1 Introduction
Feature Summary
Pin Configuration
Pin Definitions and Functions
Textual Convention
Reserved, Undefined and Unimplemented Terminology
Acronyms
2 Processor Architecture
Functional Description
CPU Register Description
Stack Pointer (SP)
Data Pointer (DPTR)
Accumulator (ACC)
B Register
Program Status Word
Extended Operation Register (EO)
Power Control Register (PCON)
Instruction Timing
3 Memory Organization
Program Memory
Data Memory
Internal Data Memory
External Data Memory
Memory Protection Strategy
Memory Protection
Flash Protection Enable
Special Function Registers
Address Extension by Mapping
Address Extension by Paging
Bit-Addressing
System Control Registers
Bit Protection Scheme
XC866 Register Overview
CPU Registers
System Control Registers
WDT Registers
Port Registers
ADC Registers
Timer 2 Registers
CCU6 Registers
SSC Registers
OCDS Registers
Boot ROM Operating Mode
User Mode
Bootstrap Loader Mode
OCDS Mode
User JTAG Mode
4 Flash Memory
Flash Memory Map
Flash Bank Sectorization
Wordline Address
Operating Modes
Error Detection and Correction
In-System Programming
In-Application Programming
Flash Programming
Flash Erasing
Aborting Flash Erase
Flash Bank Read Status
5 Interrupt System
Interrupt Structure 1
Interrupt Structure 2
Interrupt Source and Vector
Interrupt Register Description
Interrupt Node Enable Registers
External Interrupt Control Registers
Interrupt Flag Registers
Interrupt Priority Registers
Interrupt Flag Overview
Interrupt Handling
Interrupt Response Time
6 Parallel Ports
General Port Operation
General Register Description
Data Register
Direction Register
Open Drain Control Register
Pull-Up/Pull-Down Device Register
Register Map
Port 0
Functions
Register Description
Port 1
Functions
Register Description
Port 2
Functions
Register Description
Port 3
Functions
Register Description
7 Power Supply, Reset and Clock Management
Power Supply System with Embedded Voltage Regulator
Reset Control
Types of Resets
Power-On Reset
Hardware Reset
Watchdog Timer Reset
Power-Down Wake-Up Reset
Brownout Reset
Module Reset Behavior
Booting Scheme
Register Description
Clock System
Clock Generation Unit
Functional Description
Clock Source Control
Clock Management
Register Description
8 Power Saving Modes
Functional Description
Idle Mode
Slow-Down Mode
Power-Down Mode
Peripheral Clock Management
Register Description
9 Watchdog Timer
Functional Description
Register Map
Register Description
10 Serial Interfaces
Uart
UART Modes
Mode 0, 8-Bit Shift Register, Fixed Baud Rate
Mode 1, 8-Bit UART, Variable Baud Rate
Mode 2, 9-Bit UART, Fixed Baud Rate
Mode 3, 9-Bit UART, Variable Baud Rate
Multiprocessor Communication
Register Description
Baud Rate Generation
Fixed Clock
Dedicated Baud-Rate Generator
Timer 1
Interfaces of UART
Lin
LIN Protocol
LIN Header Transmission
Automatic Synchronization to the Host
Baud Rate Detection of LIN
High-Speed Synchronous Serial Interface
General Operation
Operating Mode Selection
Full-Duplex Operation
Half-Duplex Operation
Continuous Transfers
Port Control
Baud Rate Generation
Error Detection Mechanisms
Interrupts
Low Power Mode
Register Mapping
Register Description
Port Input Select Register
Configuration Register
Baud Rate Timer Reload Register
Transmit and Receive Buffer Register
11 Timers
Timer 0 and Timer 1
Basic Timer Operations
Timer Modes
Mode 0
Mode 1
Mode 2
Mode 3
Register Description
Timer 2
Auto-Reload Mode
Up/Down Count Disabled
Up/Down Count Enabled
Capture Mode
External Interrupt Function
Low Power Mode
Register Map
Register Description
12 Capture/Compare Unit 6
Functional Description
Timer T12
Timer Configuration
Counting Rules
Switching Rules
Compare Mode of T12
Duty Cycle of 0% and 100
Dead-Time Generation
Capture Mode
Single-Shot Mode
Hysteresis-Like Control Mode
Timer T13
Timer Configuration
Compare Mode
Single-Shot Mode
Synchronization of T13 to T12
Modulation Control
Trap Handling
Multi-Channel Mode
Hall Sensor Mode
Sampling of the Hall Pattern
Brushless-DC Control
Interrupt Generation
Low Power Mode
Port Connection
Register Map
Register Description
System Registers
Port Input Selection
Timer T12 - Related Registers
Timer T13 - Related Registers
Capture/Compare Control Registers
Modulation Control Registers
Global Module Control
Multi-Channel Control
Interrupt Control Registers
13 Analog-To-Digital Converter
Structure Overview
Clocking Scheme
Conversion Timing
Low Power Mode
Functional Description
Request Source Arbiter
Conversion Start Modes
Channel Control
Sequential Request Source
Overview
Request Source Control
Parallel Request Source
Overview
Request Source Control
External Trigger
Software Control
Autoscan
Wait-For-Read Mode
Result Generation
Overview
Limit Checking
Data Reduction Filter
Result Register View
Interrupts
Event Interrupts
Channel Interrupts
External Trigger Inputs
ADC Module Initialization Sequence
Register Map
Register Description
General Function Registers
Priority and Arbitration Register
External Trigger Control Register
Channel Control Registers
Input Class Register
Sequential Source Registers
Parallel Source Registers
Result Registers
Interrupt Registers
14 On-Chip Debug Support
Functional Description
Debugging
Debug Events
Hardware Breakpoints
Software Breakpoints
External Breaks
NMI-Mode Priority over Debug-Mode
Debug Actions
Call the Monitor Program
Activate the MBC Pin
Register Description
JTAG ID Register
Input Select Register
15 Bootstrap Loader
Communication Protocol
UART Transfer Block Structure
LIN Transfer Block Structure
Response Code to the Host
Bootstrap Loader Via UART
Communication Structure
The Selection of Modes
The Activation of Modes 0 and 2
The Activation of Modes 1, 3 and F
The Activation of Mode 4
Bootstrap Loader Via LIN
Communication Structure
The Selection of Modes
LIN Response Protocol to the Host
Fast LIN BSL
After-Reset Conditions
User Defined Parameters for LIN BSL
16 Index
Keyword Index
Register Index
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User's Manual, V 1 .3, Feb. 2007
XC866
8 - B i t S i n g l e C h i p M i c r o c o n t r o l l e r
M i c r o c o n t r o l l e r s
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